coregen.log

系数为4的扰码生成器

# Xilinx CORE Generator 6.1i
# User = gaolig
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in H:\file\通信ASIC课程设计\pn_code\coregen.log
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=H:\file\通信ASIC课程设计\pn_code
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=VHDL
# xilinxfamily=Virtex2
# outputoption=DesignFlow
# overwritefiles=Default
# simvendor=ModelSim
# expandedprojectpath=H:\file\通信ASIC课程设计\pn_code
SETPROJECT .
Set current Project to H:\file\通信ASIC课程设计\pn_code
SET BusFormat = BusFormatAngleBracketNotRipped
SETXIPCPORTHOST 1966
XIPCPJSENDCORES spartan2