nco_v7_1_import.entityimport

NCO的VHDL程序

<?xml version="1.0" encoding="UTF-8" standalone="no" ?><entity name="nco_v7_1_import"><interface bustype="wire" clock="clk" direction="end" name="clken"><port direction="Input" name="clken" role="wire" vhdl-type="STD_LOGIC" width="1"/></interface><interface bustype="wire" clock="clk" direction="end" name="phi_inc_i"><port direction="Input" name="phi_inc_i" role="wire" vhdl-type="STD_LOGIC_VECTOR" width="32"/></interface><interface bustype="wire" clock="clk" direction="end" name="reset_n"><port direction="Input" name="reset_n" role="wire" vhdl-type="STD_LOGIC" width="1"/></interface><interface bustype="wire" clock="clk" direction="start" name="fsin_o"><port direction="Output" name="fsin_o" role="wire" vhdl-type="STD_LOGIC_VECTOR" width="10"/></interface><interface bustype="wire" clock="clk" direction="start" name="out_valid"><port direction="Output" name="out_valid" role="wire" vhdl-type="STD_LOGIC" width="1"/></interface><hdl><native hdl-name="nco_v7_1" language="VHDL"/></hdl></entity>