elec_lock.map.qmsg

本程序是用VHDL语言实现电子密码锁功能,整个系统分为三大模块,一为控制模块,二为键盘显示模块,三为处理模块

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 06 10:38:32 2007 " "Info: Processing started: Mon Aug 06 10:38:32 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off elec_lock -c elec_lock " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off elec_lock -c elec_lock" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../debouncing/debouncing.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../debouncing/debouncing.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 debouncing-a " "Info: Found design unit 1: debouncing-a" {  } { { "../debouncing/debouncing.vhd" "" { Text "F:/备赛资料/VHDL模块/debouncing/debouncing.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 debouncing " "Info: Found entity 1: debouncing" {  } { { "../debouncing/debouncing.vhd" "" { Text "F:/备赛资料/VHDL模块/debouncing/debouncing.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "elec_lock.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file elec_lock.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 elec_lock-a " "Info: Found design unit 1: elec_lock-a" {  } { { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 25 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 elec_lock " "Info: Found entity 1: elec_lock" {  } { { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "elec_lock " "Info: Elaborating entity \"elec_lock\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "CLK_DEBOUNCE elec_lock.vhd(33) " "Warning (10036): Verilog HDL or VHDL warning at elec_lock.vhd(33): object \"CLK_DEBOUNCE\" assigned a value but never read" {  } { { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 33 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "SEL elec_lock.vhd(40) " "Info (10035): Verilog HDL or VHDL information at elec_lock.vhd(40): object \"SEL\" declared but not used" {  } { { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 40 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "OUT_NUMB elec_lock.vhd(41) " "Warning (10036): Verilog HDL or VHDL warning at elec_lock.vhd(41): object \"OUT_NUMB\" assigned a value but never read" {  } { { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 41 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "OUT_FUNC elec_lock.vhd(42) " "Warning (10036): Verilog HDL or VHDL warning at elec_lock.vhd(42): object \"OUT_FUNC\" assigned a value but never read" {  } { { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 42 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "BB elec_lock.vhd(46) " "Warning (10036): Verilog HDL or VHDL warning at elec_lock.vhd(46): object \"BB\" assigned a value but never read" {  } { { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 46 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "S elec_lock.vhd(66) " "Info (10035): Verilog HDL or VHDL information at elec_lock.vhd(66): object \"S\" declared but not used" {  } { { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 66 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CLK_KEYBOARD elec_lock.vhd(114) " "Warning (10492): VHDL Process Statement warning at elec_lock.vhd(114): signal \"CLK_KEYBOARD\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 114 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "C elec_lock.vhd(114) " "Warning (10492): VHDL Process Statement warning at elec_lock.vhd(114): signal \"C\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 114 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "R1 elec_lock.vhd(147) " "Warning (10492): VHDL Process Statement warning at elec_lock.vhd(147): signal \"R1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 147 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "R0 elec_lock.vhd(147) " "Warning (10492): VHDL Process Statement warning at elec_lock.vhd(147): signal \"R0\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 147 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "RR2 elec_lock.vhd(148) " "Warning (10492): VHDL Process Statement warning at elec_lock.vhd(148): signal \"RR2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 148 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "D0 elec_lock.vhd(154) " "Info (10035): Verilog HDL or VHDL information at elec_lock.vhd(154): object \"D0\" declared but not used" {  } { { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 154 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "D1 elec_lock.vhd(154) " "Info (10035): Verilog HDL or VHDL information at elec_lock.vhd(154): object \"D1\" declared but not used" {  } { { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 154 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "debouncing debouncing:\\debounuing:U1 " "Info: Elaborating entity \"debouncing\" for hierarchy \"debouncing:\\debounuing:U1\"" {  } { { "elec_lock.vhd" "\\debounuing:U1" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 89 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "F\[1\] data_in GND " "Warning: Reduced register \"F\[1\]\" with stuck data_in port to stuck value GND" {  } { { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 131 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "\\counter:Q\[0\]~0 23 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=23) from the following logic: \"\\counter:Q\[0\]~0\"" {  } {  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/alt_counter_f10ke.tdf" 250 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "LED_COM VCC " "Warning: Pin \"LED_COM\" stuck at VCC" {  } { { "elec_lock.vhd" "" { Text "F:/备赛资料/VHDL模块/elec_lock/elec_lock.vhd" 15 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "164 " "Info: Implemented 164 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "37 " "Info: Implemented 37 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "123 " "Info: Implemented 123 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 06 10:38:37 2007 " "Info: Processing ended: Mon Aug 06 10:38:37 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}