代码搜索：VHDL
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www.eeworm.com/read/210234/15203161
prj pingche.prj
<mark>vhdl</mark> work fpq1s.<mark>vhdl</mark>
<mark>vhdl</mark> work fpq2ms.<mark>vhdl</mark>
<mark>vhdl</mark> work jsq1.<mark>vhdl</mark>
<mark>vhdl</mark> work jsq2.<mark>vhdl</mark>
<mark>vhdl</mark> work jsq3.<mark>vhdl</mark>
<mark>vhdl</mark> work jsq4.<mark>vhdl</mark>
<mark>vhdl</mark> work jsq5.<mark>vhdl</mark>
<mark>vhdl</mark> work jsq6.<mark>vhdl</mark>
<mark>vhdl</mark> work jsq.vh ...
www.eeworm.com/read/210234/15203248
log __projnav.log
Project Navigator Auto-Make Log File
-------------------------------------
Started process "Create Schematic Symbol".
Compiling vhdl file f:/zengzhenhu/vhdl/pingche/jsq1.vhdl in Library work.
Ent
www.eeworm.com/read/210233/15203389
prj qd.prj
<mark>vhdl</mark> work ch41a.<mark>vhdl</mark>
<mark>vhdl</mark> work feng1.<mark>vhdl</mark>
<mark>vhdl</mark> work fpq1s.<mark>vhdl</mark>
<mark>vhdl</mark> work lock.<mark>vhdl</mark>
<mark>vhdl</mark> work sel.<mark>vhdl</mark>
<mark>vhdl</mark> work ymq.<mark>vhdl</mark>
<mark>vhdl</mark> work djs.<mark>vhdl</mark>
<mark>vhdl</mark> work fpq01ms.<mark>vhdl</mark>
<mark>vhdl</mark> work xzq3.< ...
www.eeworm.com/read/210233/15203401
syr qd.syr
Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.84 s | Elapsed : 0.00 / 1.00 s
--> Parameter xsthdpdir set to
www.eeworm.com/read/210233/15203533
log coregen.log
# Xilinx CORE Generator 6.2i
# User = zsx
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in E:\VHDL\waitpast\qiangdaqi4ren\coregen.log
# busformat=BusFo
www.eeworm.com/read/210233/15203557
prm qd.prm
PROMGEN: Xilinx Prom Generator G.28
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
promgen -w -p mcs -c FF -o e:\vhdl\waitpast\qiangdaqi4ren//qd -u 0 E:\VHDL\waitpast\qiangdaqi4ren\qdkz
www.eeworm.com/read/210233/15203568
prj qdkz.prj
<mark>vhdl</mark> work ch41a.<mark>vhdl</mark>
<mark>vhdl</mark> work djs.<mark>vhdl</mark>
<mark>vhdl</mark> work fpq01ms.<mark>vhdl</mark>
<mark>vhdl</mark> work feng1.<mark>vhdl</mark>
<mark>vhdl</mark> work fpq1s.<mark>vhdl</mark>
<mark>vhdl</mark> work lock.<mark>vhdl</mark>
<mark>vhdl</mark> work sel.<mark>vhdl</mark>
<mark>vhdl</mark> work xzq3.<mark>vhdl</mark>
<mark>vhdl</mark> work ymq.< ...
www.eeworm.com/read/210232/15203610
ref hdllib.ref
AR dianzheng behavioral E:/zsx/dianzheng/dianzheng.vhf sub00/vhpl09
AR chw behavioral E:/zsx/dianzheng/chw.vhdl sub00/vhpl01
EN chw NULL E:/zsx/dianzheng/chw.vhdl sub00/vhpl00
AR cont behavioral E:
www.eeworm.com/read/210232/15203631
syr dianzheng.syr
Release 6.3i - xst G.38
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.98 s | Elapsed : 0.00 / 1.00 s
--> Parameter xsthdpdir set to
www.eeworm.com/read/209612/15216446
qmsg seg73.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: