hdllib.ref

8*8点阵的实现

AR dianzheng behavioral E:/zsx/dianzheng/dianzheng.vhf sub00/vhpl09
AR chw behavioral E:/zsx/dianzheng/chw.vhdl sub00/vhpl01
EN chw NULL E:/zsx/dianzheng/chw.vhdl sub00/vhpl00
AR cont behavioral E:/zsx/dianzheng/cont.vhdl sub00/vhpl05
AR fpq2ms behavioral E:/zsx/dianzheng/fpq2ms.vhdl sub00/vhpl15
AR cnta behavioral E:/zsx/dianzheng/cnta.vhdl sub00/vhpl03
EN dz_scan NULL E:/zsx/dianzheng/lie_scan.vhdl sub00/vhpl10
EN fpq2ms NULL E:/zsx/dianzheng/fpq2ms.vhdl sub00/vhpl14
EN fpq10ms NULL E:/VHDL/waitpast/dianzheng/fpq10ms.vhdl sub00/vhpl06
AR fpq10ms behavioral E:/VHDL/waitpast/dianzheng/fpq10ms.vhdl sub00/vhpl07
EN dianzheng NULL E:/zsx/dianzheng/dianzheng.vhf sub00/vhpl08
AR hong_lv hong_lv_arch E:/zsx/dianzheng/colour_control.vhdl sub00/vhpl13
EN hong_lv NULL E:/zsx/dianzheng/colour_control.vhdl sub00/vhpl12
EN cnta NULL E:/zsx/dianzheng/cnta.vhdl sub00/vhpl02
AR dz_scan dz_scan_arch E:/zsx/dianzheng/lie_scan.vhdl sub00/vhpl11
EN cont NULL E:/zsx/dianzheng/cont.vhdl sub00/vhpl04