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简易数字频率计

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Started process "Create Schematic Symbol".

Compiling vhdl file f:/zengzhenhu/vhdl/pingche/jsq1.vhdl in Library work.
Entity <jsq1> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



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Started process "Create Schematic Symbol".

Compiling vhdl file f:/zengzhenhu/vhdl/pingche/jsq2.vhdl in Library work.
Entity <jsq2> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file f:/zengzhenhu/vhdl/pingche/jsq3.vhdl in Library work.
Entity <jsq3> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



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-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file f:/zengzhenhu/vhdl/pingche/jsq4.vhdl in Library work.
Entity <jsq4> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file f:/zengzhenhu/vhdl/pingche/jsq5.vhdl in Library work.
Entity <jsq5> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file f:/zengzhenhu/vhdl/pingche/jsq6.vhdl in Library work.
Entity <jsq6> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file f:/zengzhenhu/vhdl/pingche/kzq.vhdl in Library work.
Entity <KZQ> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file f:/zengzhenhu/vhdl/pingche/xzq.vhdl in Library work.
Entity <SZQ> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file f:/zengzhenhu/vhdl/pingche/ymq.vhdl in Library work.
Entity <YMQ> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file f:/zengzhenhu/vhdl/pingche/fpq2ms.vhdl in Library work.
Entity <fpq2ms> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file f:/zengzhenhu/vhdl/pingche/scq.vhdl in Library work.
Entity <SCQ> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file f:/zengzhenhu/vhdl/pingche/s_6.vhdl in Library work.
Entity <S_6> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file f:/zengzhenhu/vhdl/pingche/fpq1s.vhdl in Library work.
Entity <fpq1s> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Release 6.2i - sch2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



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Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".

WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 58
   days, this program will not operate. For more information about this product,
   please refer to the Evaluation Agreement, which was shipped to you along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact your local
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to: [e-mail]
   Thank You!

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file f:/zengzhenhu/vhdl/pingche/jsq1.vhdl in Library work.
Architecture behavioral of Entity jsq1 is up to date.
Compiling vhdl file f:/zengzhenhu/vhdl/pingche/jsq2.vhdl in Library work.
Architecture behavioral of Entity jsq2 is up to date.
Compiling vhdl file f:/zengzhenhu/vhdl/pingche/jsq3.vhdl in Library work.
Architecture behavioral of Entity jsq3 is up to date.
Compiling vhdl file f:/zengzhenhu/vhdl/pingche/jsq4.vhdl in Library work.
Architecture behavioral of Entity jsq4 is up to date.
Compiling vhdl file f:/zengzhenhu/vhdl/pingche/jsq5.vhdl in Library work.
Architecture behavioral of Entity jsq5 is up to date.
Compiling vhdl file f:/zengzhenhu/vhdl/pingche/jsq6.vhdl in Library work.
Architecture behavioral of Entity jsq6 is up to date.
Compiling vhdl file f:/zengzhenhu/vhdl/pingche/jsq.vhf in Library work.
Entity <jsq> (Architecture <BEHAVIORAL>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <jsq> (Architecture <BEHAVIORAL>).
Entity <jsq> analyzed. Unit <jsq> generated.

Analyzing Entity <jsq1> (Architecture <behavioral>).
Entity <jsq1> analyzed. Unit <jsq1> generated.

Analyzing Entity <jsq2> (Architecture <behavioral>).
Entity <jsq2> analyzed. Unit <jsq2> generated.

Analyzing Entity <jsq3> (Architecture <behavioral>).
Entity <jsq3> analyzed. Unit <jsq3> generated.

Analyzing Entity <jsq4> (Architecture <behavioral>).
Entity <jsq4> analyzed. Unit <jsq4> generated.

Analyzing Entity <jsq5> (Architecture <behavioral>).
Entity <jsq5> analyzed. Unit <jsq5> generated.

Analyzing Entity <jsq6> (Architecture <behavioral>).
Entity <jsq6> analyzed. Unit <jsq6> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <jsq6>.
    Related source file is f:/zengzhenhu/vhdl/pingche/jsq6.vhdl.
    Found 4-bit up counter for signal <D6>.
    Summary:
	inferred   1 Counter(s).
Unit <jsq6> synthesized.


Synthesizing Unit <jsq5>.
    Related source file is f:/zengzhenhu/vhdl/pingche/jsq5.vhdl.
    Found 4-bit up counter for signal <D5>.
    Found 1-bit register for signal <COUT>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <jsq5> synthesized.


Synthesizing Unit <jsq4>.
    Related source file is f:/zengzhenhu/vhdl/pingche/jsq4.vhdl.
    Found 4-bit up counter for signal <D4>.
    Found 1-bit register for signal <COUT>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <jsq4> synthesized.


Synthesizing Unit <jsq3>.
    Related source file is f:/zengzhenhu/vhdl/pingche/jsq3.vhdl.
    Found 4-bit up counter for signal <D3>.
    Found 1-bit register for signal <COUT>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <jsq3> synthesized.


Synthesizing Unit <jsq2>.
    Related source file is f:/zengzhenhu/vhdl/pingche/jsq2.vhdl.
    Found 4-bit up counter for signal <D2>.
    Found 1-bit register for signal <COUT>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <jsq2> synthesized.


Synthesizing Unit <jsq1>.
    Related source file is f:/zengzhenhu/vhdl/pingche/jsq1.vhdl.
    Found 4-bit up counter for signal <D1>.
    Found 1-bit register for signal <COUT>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <jsq1> synthesized.


Synthesizing Unit <jsq>.
    Related source file is f:/zengzhenhu/vhdl/pingche/jsq.vhf.
Unit <jsq> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...