seg73.map.qmsg

7 段数码管实验（包括两个实验） ７段数码管测试实验１：以动态扫描方式在８位数码管“同时”显示０—7

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 18 12:13:59 2006 " "Info: Processing started: Sat Feb 18 12:13:59 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off seg73 -c seg73 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off seg73 -c seg73" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seg73.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file seg73.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 seg73-arch " "Info: Found design unit 1: seg73-arch" {  } { { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 17 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 seg73 " "Info: Found entity 1: seg73" {  } { { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 9 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "seg73 " "Info: Elaborating entity \"seg73\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "seg73.vhd(180) " "Info: VHDL Case Statement information at seg73.vhd(180): OTHERS choice is never selected" {  } { { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 180 0 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "dataout\[0\] VCC " "Warning: Pin \"dataout\[0\]\" stuck at VCC" {  } { { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 13 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 21 -1 0 } } { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 21 -1 0 } } { "seg73.vhd" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/vhdl/接口实验/7段数码管/seg73/seg73.vhd" 21 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "95 " "Info: Implemented 95 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "81 " "Info: Implemented 81 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 18 12:14:03 2006 " "Info: Processing ended: Sat Feb 18 12:14:03 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}