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VHDL 的代码
vhdl.vhd
-- generated by newgenasym Thu Oct 23 15:04:42 2008
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity ic574 is
port (
C1: IN STD_LOGIC;
D0: IN
vhdl.vhd
-- generated by newgenasym Thu Oct 30 14:40:37 2008
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity lt3080 is
port (
\in\: IN STD_LOGIC;
OUT1: OUT
vhdl.txt
5-1
main.vhdl
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity topclock is
Port(clk,reset:in std_logic;
--S1,m1,h1:in std_logic_vector(7 downto