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VHDL 的代码
swep_fre.prj
vhdl work "swep_fre.vhd"
sincos.prj
vhdl work "sincos.vhd"
findcos.prj
vhdl work "sincos.vhd"
vhdl work "findcos.vhd"
findsin.prj
vhdl work "sincos.vhd"
vhdl work "findsin.vhd"
readme.txt
注1： 含有不可综合语句，请自行修改
注2： 一些PLD只允许I/O口对外三态，不支持内部三态，使用时要注意
注3: 设计RAM的最好方法是利用器件厂家提供的软件自动生成RAM元件，并在VHDL程序中例化
将16进制转化为std_logic.txt
VHDL: Converting a Hexadecimal Value to a Standard Logic Vector
This example shows how to convert a hexadecimal value to a std_logic_vector.
It is shown in both VHDL '87 (IEEE Std 1076-1987) and
将16进制转化为std_logic.txt
VHDL: Converting a Hexadecimal Value to a Standard Logic Vector
This example shows how to convert a hexadecimal value to a std_logic_vector.
It is shown in both VHDL '87 (IEEE Std 1076-1987) and
vhdl三分频程序.txt
发一个3分频的VHDL程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY Odd_Fren is
port(Clk : in std_logic;
O : out std_logic);
end Odd_Fren;
architecture
modelsim testbench vhdl参考模板.vhd
-- VHDL Test Bench Created from source file fifo_new.vhd -- 10:13:22 04/05/2005
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for
bookinfo.dat
[General Information]
书名=VHDL与FPGA设计
作者=
页数=317
SS号=11086666
出版日期=