main.vhdl

EDA课程设计（带完整设计报告）

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity topclock is
 Port(clk,reset:in std_logic;
--S1,m1,h1:in std_logic_vector(7 downto 0);
--D1: in std_logic_vector(2 downto 0);
Alarm:out std_logic;
Sec1,sec2,min1,min2,hou1,hou2:buffer std_logic_vector(3 downto 0);
s1,s2,m1,m2,h1,h2:out std_logic_vector(6 downto 0));
--Day:out std_logic_vector(2 downto 0));
End;
Architecture one of topclock is

Component second1                                        --秒元件的例化
Port(clks,reset: in std_logic;
           --S1: in std_logic_vector(7 downto 0);        
           Sec1,sec2:buffer std_logic_vector(3 downto 0);
           Ensec:out std_logic);
End Component;

Component minute1                                        --分元件的例化
Port(clkm,reset: in std_logic;
           --m1: in std_logic_vector(7 downto 0);
           min1,min2:buffer std_logic_vector(3 downto 0);
           Enmin:out std_logic);
End Component;

Component hour1                                          --时元件的例化
Port(clkh,reset: in std_logic;
           --h1: in std_logic_vector(7 downto 0);
           hou1,hou2:buffer std_logic_vector(3 downto 0));
           --Enhour:out std_logic);
End Component;

Component yima                                           --星期元件的例化
Port(sec1,sec2,min1,min2,hou1,hou2: in std_logic_vector(3 downto 0);
s1,s2,m1,m2,h1,h2:out std_logic_vector(6 downto 0)); 
End Component;

Component alarm1                                         --报时元件的例化
Port(reset: in std_logic;
           min1,min2: in std_logic_vector(3 downto 0);
           alarm:out std_logic);
End Component;
Component jhgjgh
port(clk,reset:in std_logic;
      q:out std_logic);
End Component;


signal enm,enh,enk:std_logic;                 --秒分、分时、时星期之间的连接信号
--signal ena:std_logic_vector(7 downto 0);             --分与报时之间的连接信号
begin
--signal cnt:integer:=0;
--signal clks : std_logic :='0';
 
--process(clk)
  --begin
  --if reset = '0' then
     --clks<= '0';
      --if(clk'event and clk='1')then   
           --if cnt=16000000 then
              --if cnt=10 then
               --cnt<=0;
	          -- clks<=not(clks);	
          --else
	          --cnt<=cnt+1;
            --end if;
  --end if;
uo:jhgjgh port map (reset=>reset,clk=>clk,q=>enk);
u1:second1 port map(reset=>reset,
sec1=>sec1, sec2=>sec2,clks=>enk, ensec=>enm);
u2:minute1 port map(reset=>reset,
min1=>min1, min2=>min2, clkm=>enm,enmin=>enh);
u3:hour1 port map(reset=>reset,
hou1=>hou1, hou2=>hou2,clkh=>enh);
u4:yima port map(sec1=>sec1,sec2=>sec2,min1=>min1,min2=>min2,hou1=>hou1,
hou2=>hou2,s1=>s1,s2=>s2,m1=>m1,m2=>m2,h1=>h1,h2=>h2);
u5:alarm1 port map(reset=>reset,min1=>min1,min2=>min2,alarm=>alarm);
end;