vhdl.vhd

来自「Cadence_Starter_Library」· VHDL 代码 · 共 27 行

-- generated by newgenasym Thu Oct 23 15:04:42 2008

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity ic574 is
    port (    
	C1:        IN     STD_LOGIC;    
	D0:        IN     STD_LOGIC;    
	D1:        IN     STD_LOGIC;    
	D2:        IN     STD_LOGIC;    
	D3:        IN     STD_LOGIC;    
	D4:        IN     STD_LOGIC;    
	D5:        IN     STD_LOGIC;    
	D6:        IN     STD_LOGIC;    
	D7:        IN     STD_LOGIC;    
	EN:        OUT    STD_LOGIC;    
	O0:        OUT    STD_LOGIC;    
	O1:        OUT    STD_LOGIC;    
	O2:        OUT    STD_LOGIC;    
	O3:        OUT    STD_LOGIC;    
	O4:        OUT    STD_LOGIC;    
	O5:        OUT    STD_LOGIC;    
	O6:        OUT    STD_LOGIC;    
	O7:        OUT    STD_LOGIC);
end ic574;