代码搜索结果

3 ~E dec24d c:\my designs\decoder\src\VHDL code2.vhd 3 ~A dataflow c:\my designs\decoder\src\VHDL code2.vhd 7

Design: 9:00 PM, Tuesday, March 31, 2009 Design: Opening design "c:\my designs\fullsubtractor\fullsubtractor.adf" Design: Error: C:\My Designs\fullsubtractor\src\VHDL code1.vhd cannot be compiled.

Compilation... File: .\src\VHDL code1.vhd Error: COMP96_0016:VHDL code1.vhd : (2, 29): Design unit declaration expected. Error: COMP96_0016:VHDL code1.vhd : (2, 30): Design unit declaration exp

MESSAGE "File: .\src\VHDL code1.vhd" ERROR COMP96_0016: "Design unit declaration expected." "c:\my designs\fullsubtractor\src\VHDL code1.vhd" 2 29 ERROR COMP96_0016: "Design unit declaration expect

[Project] Current config=Generic VCS=0 modified=3 [Configurations] Generic=dff [Files] /VHDL code4.vhd=4, 1 29995544 1718645976, 0, , , ,

[Files List] c:\program files\aldec\active-vhdl\vlib\std\src\standard.vhd=S c:\program files\aldec\active-vhdl\vlib\ieee\src\stdlogic.vhd=S c:\my designs\dff\src\VHDL code4.vhd=S

3 ~E ffD c:\my designs\dff\src\VHDL code4.vhd 3 ~A behav c:\my designs\dff\src\VHDL code4.vhd 7

Design: 9:42 PM, Tuesday, March 31, 2009 Design: Opening design "c:\my designs\mux81\mux81.adf" Design: Error: C:\My Designs\mux81\src\VHDL code7.vhd cannot be compiled. Compilation... File: .\src

3 ~E mux c:\my designs\mux81\src\VHDL code7.vhd 5 ~A mux c:\my designs\mux81\src\VHDL code7.vhd 12

[Project] Current config=Generic VCS=0 modified=2 [Configurations] Generic=mux81 [Files] /VHDL code7.vhd=4, 1 29995547 2383900338, 0, , , ,