vhdl.sct

c#设计模式WithCla

NO_OUTPUT_BEGIN
This New release of VHDL script file is limited to Simple VHDL Entity Declaration.
Class object are translate into Package, component, Entity, Achitecture
Procedure with or without preconditions are translate into process

Clerbois Michel 01/10/96 REV 1.0c       01/15/96
NO_OUTPUT_END

-- This VHDL Source Have been create with WITHCLASS95
-- Scrip file written by Clerbois M

use  WORK.WCLASSPKG.ALL; -- Definition 

package CLASS_NAME$PKG is
    COMPONENT CLASS_NAME
	PORT (
--      CLOCK,RESET:IN BIT; only for synchronous object
SELECT_WHEN ATTRIBUTE_ACCESS == public [ ATTRIBUTE_NAME :  ATTRIBUTE_TYPE ;DELETE_LAST_SYMBOL] );
	END COMPONENT;
END CLASS_NAME$PKG;

use  WORK.WCLASSPKG.ALL; -- Definition 

ENTITY  CLASS_NAME is 
	PORT (
--      CLOCK,RESET:IN BIT; only for synchronous object
SELECT_WHEN ATTRIBUTE_ACCESS == public  [ ATTRIBUTE_NAME :  ATTRIBUTE_TYPE ;DELETE_LAST_SYMBOL] );
END CLASS_NAME;

use  WORK.WCLASSPKG.ALL; -- Definition 
[use WORK.$AGGREGATION_MANY_CLASS$PKG.ALL ;]
[use WORK.$AGGREGATION_ONE_CLASS$PKG.ALL ;]

ARCHITECTURE FSM$CLASS_NAME OF CLASS_NAME IS
SELECT_WHEN ATTRIBUTE_IS_CONSTANT [const ATTRIBUTE_NAME : ATTRIBUTE_TYPE := ATTRIBUTE_INITIAL_VALUE;]
SELECT_WHEN ATTRIBUTE_ACCESS == private [SIGNAL ATTRIBUTE_NAME : ATTRIBUTE_TYPE;]

BEGIN
--Insert NOT State machine Process here
-- process 

-- AGGREGATION of MANY TO MANY == instantation of objects
-- copy the lines N times and modify the parameters
[ AGGREGATION_MANY_NAME : AGGREGATION_MANY_CLASS PORT MAP( -- list of signals ) ; 
-- or use or loop
-- L1:FOR I in 1 to N GENERATE
-- 	AGGREGATION_MANY_NAME$_N : AGGREGATION_MANY_CLASS PORT MAP( -- list of signals ) ; 
--	end generate;
]

-- AGGREGATION of ONE TO ONE == instantation of an object
-- Generate the instantiation line and modify the parameters
[ AGGREGATION_ONE_NAME : AGGREGATION_ONE_CLASS PORT MAP( -- list of signals ) ; ]

[OPERATION_NAME:PROCESS OPERATION_PRECONDITION
begin
  OPERATION_CODE
end PROCESS OPERATION_NAME;
]

-- begin
-- end process;

-- Insert here the process source file generated with state code report (cut and paste)
-- Use the script file vhdlst.sct to generate the state machine

END FSM$CLASS_NAME;