top.vhdl

本代码介绍了使用VHDL开发FPGA的一般流程

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;


entity Top is
      Port (   
			CLK_Basic         	:In    std_logic;	-- 32MHz
			CLK			   	:In	std_logic;	--被测信号
			RST				:IN std_logic;				    --强制清零信号,0有效
 			Switch		   	:In  std_logic_vector(2 downto 0);
			LED_point			:OUT std_logic_vector(0 to 2);
			LED6_SEG,LED5_SEG,LED4_SEG,LED3_SEG,LED2_SEG,LED1_SEG			:OUT std_logic_vector(6 downto 0);
			OVER				:OUT std_logic;
			LED_gate			:OUT std_logic	 			--时间闸信号指示灯，随时间闸的长短而闪烁
	      );

end Top;

architecture behavior of Top is

attribute clock_buffer:string;
attribute clock_buffer of CLK:signal is "bufGP";


Signal CP1,CP10,CP100,CP10k,CP	:std_logic;
Signal gate0,Reset,LOAD   		:std_logic;
Signal OVER0,OVER1   			:std_logic;
Signal F,E,D,C,B,A				:STD_LOGIC_VECTOR(3 downto 0);
Signal BCD_6,BCD_5,BCD_4,BCD_3,BCD_2,BCD_1	:STD_LOGIC_VECTOR(3 downto 0);

   
component Freq_Change is
	Port(
		clk_in		:in STD_LOGIC;				--输入时钟脉冲
		clk_out1		:out STD_LOGIC;			--输出频率1HZ时钟脉冲
		clk_out10		:out STD_LOGIC;			--输出频率10HZ时钟脉冲
		clk_out100	:out STD_LOGIC;			--输出频率100HZ时钟脉冲
		CP10k		:out STD_LOGIC				--输出频率10KHZ时钟脉冲
	);
end component;

component Control_Unite is
	PORT(
			Switch			:IN std_logic_vector(0 to 2);	   
			clk1,clk10,clk100	:IN std_logic;
			RST				:IN std_logic;				   
			gate,CLEAR,LOAD   	:OUT std_logic;			   
			LED_point			:OUT std_logic_vector(0 to 2)	   
	   );
end component;

component GATE 	is
	PORT(
		CLK,gate0		:IN STD_LOGIC;
		CP		  	:OUT STD_LOGIC
	);
end component;

component Counter is
PORT(
	Reset,clk			:IN STD_LOGIC;
	OVER 			:OUT STD_LOGIC;
	F,E,D,C,B,A		:OUT STD_LOGIC_VECTOR(3 downto 0) 
);
end component;

component Data_Lock is
	PORT(
		OVER_in,LOAD						:IN STD_LOGIC;
		F,E,D,C,B,A 						:IN STD_LOGIC_VECTOR(3 downto 0);
		OVER								:OUT STD_LOGIC;
		BCD_6,BCD_5,BCD_4,BCD_3,BCD_2,BCD_1	:OUT STD_LOGIC_VECTOR(3 downto 0)
	);
end component;

component BCD2SEG_Display is
	PORT(
		BCD_6,BCD_5,BCD_4,BCD_3,BCD_2,BCD_1	:IN STD_LOGIC_VECTOR(3 downto 0);
		CP,OVER_flow						:IN STD_LOGIC;
		SEG_6,SEG_5,SEG_4,SEG_3,SEG_2,SEG_1	:OUT STD_LOGIC_VECTOR(6 downto 0)
	);
end component;

begin

U0:Freq_change port map(clk_in=>CLK_Basic,clk_out1=>CP1,clk_out10=>CP10,clk_out100=>CP100,CP10k=>CP10k);


U1:Control_Unite port map(Switch=>Switch,clk1=>CP1,clk10=>CP10,clk100=>CP100,RST=>RST,gate=>gate0,CLEAR=>Reset,LOAD=>LOAD,LED_point=>LED_point);


U2:GATE port map(CLK=>CLK,gate0=>gate0,CP=>CP);


U3:Counter port map(Reset=>Reset,clk=>CP,OVER=>OVER0,F=>F,E=>E,D=>D,C=>C,B=>B,A=>A);


U4:Data_Lock port map(OVER_in=>OVER0,LOAD=>LOAD,F=>F,E=>E,D=>D,C=>C,B=>B,A=>A,OVER=>OVER1,BCD_6=>BCD_6,BCD_5=>BCD_5,BCD_4=>BCD_4,BCD_3=>BCD_3,BCD_2=>BCD_2,BCD_1=>BCD_1);


U5:BCD2SEG_Display port map(BCD_6=>BCD_6,BCD_5=>BCD_5,BCD_4=>BCD_4,BCD_3=>BCD_3,BCD_2=>BCD_2,BCD_1=>BCD_1,CP=>CP10k,OVER_flow=>OVER1,SEG_6=>LED6_SEG,SEG_5=>LED5_SEG,SEG_4=>LED4_SEG,SEG_3=>LED3_SEG,SEG_2=>LED2_SEG,SEG_1=>LED1_SEG);

LED_gate<=gate0;

OVER<=OVER1;
end behavior;