counter.vhdl

本代码介绍了使用VHDL开发FPGA的一般流程

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Counter is
PORT(
	Reset,clk			:IN STD_LOGIC;
	OVER 			:OUT STD_LOGIC;				 --OVER为0时表示有溢出
	F,E,D,C,B,A		:OUT STD_LOGIC_VECTOR(3 downto 0) 
);
end Counter;

architecture Behavioral of Counter is

component counter10	is
	PORT(
		Reset,CLK  		:IN STD_LOGIC;	
		carry_out  		:OUT STD_LOGIC;	
		count_BCD_out 		:OUT STD_LOGIC_VECTOR(3 downto 0)
		);
end component;
Signal S1,S2,S3,S4,S5,carry	:STD_LOGIC;

begin
	U0:counter10 port map(Reset=>Reset,CLK=>clk,carry_out=>S1,count_BCD_out=>A);
	U1:counter10 port map(Reset=>Reset,CLK=>S1,carry_out=>S2,count_BCD_out=>B);
	U2:counter10 port map(Reset=>Reset,CLK=>S2,carry_out=>S3,count_BCD_out=>C);
	U3:counter10 port map(Reset=>Reset,CLK=>S3,carry_out=>S4,count_BCD_out=>D);
	U4:counter10 port map(Reset=>Reset,CLK=>S4,carry_out=>S5,count_BCD_out=>E);
	U5:counter10 port map(Reset=>Reset,CLK=>S5,carry_out=>carry,count_BCD_out=>F);

process(Reset,carry)
begin
if 	Reset='0'		then
	OVER<='1';
elsif 	falling_edge(carry)	then
	OVER<='0';
end if;
end process;

end Behavioral;