代码搜索结果

[Files List] c:\program files\aldec\active-vhdl\vlib\std\src\standard.vhd=S c:\program files\aldec\active-vhdl\vlib\ieee\src\stdlogic.vhd=S c:\my designs\comparator\src\VHDL code1.vhd=S

3 ~E comp4b c:\my designs\comparator\src\VHDL code1.vhd 4 ~A behav c:\my designs\comparator\src\VHDL code1.vhd 8

VHDL Code: Behavioral model: LIBRARY IEEE;//standard library USE IEEE.STD_LOGIC_1164.ALL;//importing the library. //entity declaration. ENTITY comp4b IS PORT(A,B:IN BIT_VECTOR(3 DOWNTO 0); F1,F2

Design: 9:35 PM, Tuesday, March 31, 2009 Design: Opening design "c:\my designs\mux21\mux21.adf" Design: Error: C:\My Designs\mux21\src\VHDL code7.vhd cannot be compiled. Compilation... File: .\src

Compilation... File: .\src\VHDL code7.vhd Compile Entity "MUX" Compile Architecture "main" of Entity "MUX" Error: COMP96_0019:VHDL code7.vhd : (1, 174): Keyword "is" expected. Error: COMP96

01000042 V MUX 5 ".\src\VHDL code7.vhd" 418 202 0 12 0 12 00000001 1 .\src\VHDL*code7.vhd 0 0 0 0 0 0 0 1 1 29 0 29 12 ~ ~ 0 0 0 67 0 1 15 ieee std_logic_1164 4 2 0 15 ieee std_logic_1164 0 0 0 0 1 29

MESSAGE "File: .\src\VHDL code7.vhd" MESSAGE "Compile Entity "MUX"" MESSAGE "Compile Architecture "main" of Entity "MUX"" ERROR COMP96_0019: "Keyword "is" expected." "c:\my designs\mux21\src\VHD

1 ~E MUX c:\my designs\mux21\src\VHDL code7.vhd 1

[Project] Current config=Generic VCS=0 modified=2 [Configurations] Generic=mux21 [Files] /VHDL code7.vhd=4, 0 29995546 2614180134, 0, , , ,

[Files List] c:\program files\aldec\active-vhdl\vlib\std\src\standard.vhd=S c:\program files\aldec\active-vhdl\vlib\ieee\src\stdlogic.vhd=S c:\my designs\decoder\src\VHDL code2.vhd=S