clkunit.vhdl

完成VHDL实现UART准确无误码传输.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity CLkUnit is
 Port(
   SysClk	:in Std_Logic;--system clk,66.6MHz

   EnableRx	:out Std_Logic;--revice sample Frequency,
   EnableTx	:out Std_Logic;--Send baudrate

	Reset		:in Std_Logic);--Reset Input
end CLkUnit;

architecture Behavioral of CLkUnit is
  signal tmpEnRx	: Std_Logic;--
  signal tmpEnTx	: Std_Logic;--

begin
---------------------------------------------------------------------------
--Dived the system clock by 36
--
---------------------------------------------------------------------------
DivClk36: process(SysClk,Reset)
--DivClk36: process(SysClk)
  constant CntOne	: unsigned(5 downto 0)	:="000001";
  variable Cnt15	:	unsigned(5 downto 0)	;
begin 
	if Rising_Edge(SysClk) then 
		if Reset = '0' then 
			Cnt15	:="000000";
 		   tmpEnRx<='0';
 		else
			Cnt15	:=Cnt15+CntOne	;
			case Cnt15 is
				when "001111" =>
				 tmpEnRx<='1';
				 Cnt15:="000000";
				when others =>
				 tmpEnRx<='0';
			end case;
		end if;
	end if;
end process ;
---------------------------------------------------------------------------
--Dived the tmpRx by 16
--
---------------------------------------------------------------------------
DivClk16: process(SysClk,Reset,tmpEnTx)
  constant CntOne	: unsigned(7 downto 0)	:="00000001";
  variable Cnt234	:	unsigned(7 downto 0)	;
begin 					    
	if Rising_Edge(SysClk) then 
	--  if SysClk'event and SysClk='1'then
		if Reset = '0' then 
			Cnt234	:="00000000";
			--ClkDiv36 <='0';
 		   tmpEnTx<='0';
--			EnableRX<='0';
 		else
			Cnt234	:=Cnt234+CntOne	;
			case Cnt234 is
				when "11101010" =>
				 tmpEnTx<='1';
--				 EnableRX<='1';
				 Cnt234:="00000000";
				when others =>
				 tmpEnTx<='0';
--				 EnableRX<='0';
			end case;
		end if;
	end if;
 END process ;
EnableRx<=tmpEnRx;
EnableTx<=tmpEnTx;
end Behavioral;