rs232.vhdl

来自「完成VHDL实现UART准确无误码传输.」· VHDL 代码 · 共 40 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity RS232 is
       port(
   		 nReset      : in std_logic;
          gCLK        : in std_logic;
			 ESX         : in std_logic_vector(9 downto 0);
			 ESY         : in std_logic_vector(8  downto 0);
			 updateESP   : in std_logic;
			 TxD         : out std_logic

);
end RS232;

architecture Behavioral of RS232 is
COMPONENT  MUART 
  port (
  	SysClk	: in Std_Logic; --systme clock
	Reset	: in Std_Logic;--System Reset
	TxD		: out Std_Logic; --Send data out
     ESX       : in std_logic_vector(9 downto 0);
     ESY       : in std_logic_vector(8 downto 0);
	updateESP   : in std_logic	
  );
end COMPONENT;
begin
U117:MUART
  port map(
  	SysClk	  =>	gClk,	 
	Reset	  =>	nReset,	 
	TxD		  =>	TxD,		 
     ESX         =>	ESX,        
     ESY         =>	ESY,        
	updateESP   =>	updateESP 
  );
end Behavioral;