txunit.vhdl

完成VHDL实现UART准确无误码传输.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TXUnit is
 port(
 		Clk	: in	Std_Logic;--System colock;
		Reset	: in  Std_Logic;--Reset Singal
		Enable 	: in Std_Logic;--Transimmit colock;
		Load	: in	Std_Logic;--Load the Data form bus to txbuffer
		TxD	: out Std_Logic;--Transmmit out
		TRegE	: out Std_Logic;--Data have been in Tranmmit Reg or send it complete
		TBufE	: out Std_Logic;--txbuffer is empty
--		DISP_SEG2 : out Std_Logic_Vector(7 downto 0);--LED Display
		DataO	: in	Std_Logic_Vector(7 downto 0)--Data in put
 );
end TXUnit;

architecture Behavioral of TXUnit is
	signal TBuff	:Std_Logic_Vector(7 downto 0);--Txbuffer,get data form the DataO;
	signal TReg		:Std_Logic_Vector(7 downto 0);--Get data form the Txbuffer,and send it sequence to TX
	signal BitCnt	:Unsigned(3 downto 0);--Counter to indicate which bit is been send to tx
	signal tmpTRegE	: Std_Logic;--TRegE buffer
	signal tmpTBufE	:Std_Logic;--TBufE buffer

begin
---------------------------------------------------------------------------
--TxUnit main descriptor
--
---------------------------------------------------------------------------
process(Clk,Reset,Enable,Load,DataO,TBuff,TReg,tmpTRegE,tmpTBufE)

	variable tmp_TRegE	:	Std_Logic;
	constant CntOne		:	Unsigned(3 downto 0):="0001";
begin 
	if Rising_Edge(Clk) then --just at rising edge send the data
		if Reset='0' then 
			tmpTRegE	<=	'1';--Rest the 
			tmpTBufE	<=	'1';
			TxD	<=	'1';
			BitCnt	<=	"0000";
			else if Load ='1'	then --load data form DataO to TxBuff
				TBuff <= DataO;	--Get Datat form the Bus
				tmpTBufE <='0';	--Indicate the Buffer have data;
				else if Enable='1' then --start send the data 
							if(tmpTBufE='0') and(tmpTRegE='1') then --Load data from TBuf to TReg,
									TReg <=TBuff; --load the data to TReg;
									tmpTBufE <='1';--
									tmpTRegE <='0';--										  			
									BitCnt	<=	"0000";
								else if tmpTRegE='0' then -- Send the Data sequence															
											case BitCnt is	--Ready to couter ,
												when "0000"	=> -- BitCnt equal 0 send start bit
												TxD <='0';-- send the start bit
												BitCnt <= BitCnt+CntOne;--increase the bit counter
												when "0001"|"0010"|"0011"|
													  "0100"|"0101"|"0110" |
													  "0111"|"1000" =>
													  TReg <= '1'& TReg(7 downto 1);--TReg left shit
													  TxD <= TReg(0);--sedn it out
 								  					  BitCnt <= BitCnt+CntOne;--increase the bit counter
  												when "1001"=>	-- send stop bit
														TxD <='1';--stop bit
														TReg <= '1'&TReg(7 downto 1);--????
														BitCnt <="0000";
														tmpTRegE <='1';--
												 when others => null;--donothing
					  						end case;
 								 end if;
			  				end if;
				  end if;
			 end if;
		  end if;
	end if;
end process;
---
	TRegE <=tmpTRegE	;
	TBufE <=tmpTBufE	;

end Behavioral;