muart.vhdl

完成VHDL实现UART准确无误码传输.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity MUART is
  port (
  	SysClk	: in Std_Logic; --systme clock
	Reset	: in Std_Logic;--System Reset
	TxD		: out Std_Logic; --Send data out
     ESX       : in std_logic_vector(9 downto 0);
     ESY       : in std_logic_vector(8 downto 0);
	updateESP   : in std_logic
  );
end MUART;

architecture Behavioral of MUART is
	Signal TxData	:	Std_Logic_Vector(7 downto 0);--
	Signal TxDatap	:	Std_Logic_Vector(7 downto 0);--
	--- add for test
--	Signal Enable_Tmp	:Std_Logic;	--Txsynoch signal

	Signal EnableRx	:Std_Logic;	--Rxsynoch signal
	Signal EnableTx	:Std_Logic;	--Txsynoch signal
	Signal DRdy			:Std_Logic;	-- Data Ready signal

	Signal TBufE		:Std_Logic;	-- inter Send register buffer is empty
	Signal FErr			:Std_Logic;	-- Frame Error
	signal OErr			:Std_Logic;	--Overwrite error
	signal Load			:Std_logic;	--Load data from the Bus to data bus
	signal TRegE		: std_logic;

	component ClkUnit is
		Port(
   		SysClk	:in Std_Logic;--system clk,66.6MHz
			EnableRx	:out Std_Logic;--revice sample Frequency,
   		EnableTx	:out Std_Logic;--Send baudrate
			Reset	:in Std_Logic--Reset Input
		);
    end component;


    component TxUnit is
	 	port(
 			Clk		: in	Std_Logic;--Transimmit colock;
			Reset	: in  Std_Logic;--Reset Singal
			Enable 	: in Std_Logic;--Enable  Input;
			Load		: in	Std_Logic;--Load the Data form bus to txbuffer
			TxD		: out Std_Logic;--Transmmit out
			TRegE	: out Std_Logic;--Data have been in Tranmmit Reg or send it complete
			TBufE	: out Std_Logic;--txbuffer is empty
			DataO	: in	Std_Logic_Vector(7 downto 0)--Data in put
 		);
    end component;
type ImProcessingState is (waitendonefield,stRdOdd,stSendingOdd,WAIT1,
								   stRdOdd1,stSendingOdd1,WAIT2,
								   stRdOddNULL,stSendingOddNULL,WAITNULL,
								   stRdOdd2,stSendingOdd2,WAIT3);
signal state_x,state_r:ImProcessingState;

begin
---------------------------------------------------------------------------
--port map
--
---------------------------------------------------------------------------
ClkDiv	:ClkUnit	port map(SysClk,EnableRX,EnableTX,Reset);
TxDev		:TxUnit 	port map(SysClk,Reset,EnableTx,Load,TxD,TRegE,TBufE,TxData);
--RxDev		:RxUnit	port map(SysClk,Reset,EnableRx,RxD,Read,FErr,OErr,DRdy,RxData);


   StateMachineUpdate:process(SysClk,Reset)
	begin
	   if Reset='0'  then	   
  		   state_r<=waitendonefield;
		elsif SysClk'event and SysClk='1' then
		   state_r<=state_x;
		end if;
	end process;
	MainProcessing: process(Reset,state_r,updateESP,TBufE,ESX, ESY)
	begin
	    case state_r is
		   when waitendonefield=>
			    if updateESP='1' then
                    state_x<=stRDodd;
				END IF;
			when stRdodd=>
 				  if (TBufE='1') then --register
					 Load<='1';
				      TxData<="000000" & ESX(9 downto 8);
				      state_x<=stSendingOdd;	  	
				  end if;
			when stSendingOdd=>
				  if(TBufE='0') then --register
				    state_x<=WAIT1;
				    Load<='0';
				  else
				    state_x<=stRdOdd1;
				  end if;
			WHEN WAIT1=>
				  state_x<=stSendingOdd;
			when stRDOdd1=>
 				  if (TBufE='1') then --register
					 Load<='1';
				      TxData<=ESX(7 DOWNTO 0);
				      state_x<=stSendingOdd1;	  	
				  end if;
			when stSendingOdd1=>
				  if(TBufE='0') then --register
				    state_x<=WAIT2;
				    Load<='0';
				  else
				    state_x<=stRdOddNULL;
				  end if;
			WHEN WAIT2=>
				  state_x<=stSendingOdd1;
			when stRDOddNULL=>
 				  if (TBufE='1') then --register
					 Load<='1';
				      TxData<="0000000" & ESY(8);
				      state_x<=stSendingOddNULL;	  	
				  end if;
			when stSendingOddNULL=>
				  if(TBufE='0') then --register
				    state_x<=WAITNULL;
				    Load<='0';
				  else
				    state_x<=stRDOdd2;
				  end if;
			WHEN WAITNULL=>
				  state_x<=stSendingOddNULL;
			 when stRDOdd2=>
 				  if (TBufE='1') then --register
					 Load<='1';
				      TxData<=ESY(7 DOWNTO 0);
				      state_x<=stSendingOdd2;	  	
				  end if;
			when stSendingOdd2=>
				  if(TBufE='0') then --register
				    state_x<=WAIT3;
				    Load<='0';
				  else
				    state_x<=waitendonefield;
				  end if;
			WHEN WAIT3=>
				  state_x<=stSendingOdd2;
			      

			when others=>
			     state_x<=waitendonefield;
		 end case;
	 -- end if;
	end process;
end Behavioral;