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VHDL 的代码
scope.vhdl
-- Name: Scope Controller
-- Version: 1.4 Partially Tested
-- Date: 06Sep2005 Adi
-- Function: XC9572 controller for eOscope
--
-- Descrition:
-- Keyboard interface, ADC control
vhdl.txt
/*端口信号说明：
clk 输入时钟信号
reset 复位信号，低电平有效
din 按键输入信号
d 波形的离散值输出*/
module wave(clk,reset,din,d);
input clk,reset,din;
output [7:0] d;
reg [7:0] d;
//中间变量寄存器
reg [7:0]
fpq.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fpq is
port(clkin:in std_logic;
clkout:out std_logic);
end fpq;
architecture
dsq.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dsq is
port
(en1,hold,clkin1:in std_logic;
q2:out std_logic;
dat
ymq.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ymq is
port
(int:in std_logic_vector(3 downto 0);
out7:out std_logic_