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找到约 10,000 项符合「VHDL」的源代码
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www.eeworm.com/read/315769/13536748
txt vhdl infrared receive.txt
接收解码部分
接收解码用<mark>VHDL</mark>语言编写程序，在EDA实验板上实现解码，要求具有以下功能：
（1）基本要求：
（a）将一体化红外接收解调器的输出信号解码（12个单击键、6个连续键，单击键编号为7－18，连续键编码为1－6），在EDA实验板上用七段数码管显示出来；
（b）当按下遥控器1—6号连续键时，在EDA实验板上用发光二极管点亮作为连续键按下的指示，要求遥控器上连续键接下时指示灯点 ...
www.eeworm.com/read/314829/13558210
vhd altera_vhdl_support.vhd
-- ----------------------------------------------------------------------------
--
-- These routines are used to help SOPC Builder generate VHDL code.
--
-- -----------------------------------
www.eeworm.com/read/314060/13575886
log ngd2vhdl.log
Release 5.1i - ngd2vhdl F.23
Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
ngd2vhdl: Reading design stopwatch.ngd ...
ngd2vhdl: Specializing design ...
ngd2vhdl: Adding the appropriate PH
www.eeworm.com/read/313792/13580874
bak vhdl2.vhd.bak
--/*******************************************************************
-- *
-- * DESCRIPTION: UART receiver module.
-- *
-- * AUTHOR: Jim Jian
-- *
-- * HISTORY: 1/14/96
-- *
--
www.eeworm.com/read/311606/13628795
doc nand2_vhdl.doc
www.eeworm.com/read/309101/13682364
txt 8255_io_vhdl.txt
可编程8255并行I/O接口芯片设计：
VHDL源程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity PI8255A is
port(
reset,rd,wr,cs,a0,a1 : in std_u
www.eeworm.com/read/308956/13686594
fit conteol_cs_vhdl.fit
-- MAX+plus II Compiler Fit File
-- Version 10.0 9/14/2000
-- Compiled: 12/14/2005 11:03:52
-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and
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cnf conteol_cs_vhdl.cnf
www.eeworm.com/read/308956/13686617
vhd conteol_cs_vhdl.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
entity conteol_cs_vhdl is
port(
P27 : in std_logic;
hwr : in std_logic;
hrd : in std_logic;
del
www.eeworm.com/read/308956/13686626