conteol_cs_vhdl.vhd

来自「在采用 320x240 屏的设计实验箱上运行」· VHDL 代码 · 共 42 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
entity conteol_cs_vhdl is
	port(
		P27		: in std_logic; 
        hwr	 	: in std_logic;
		hrd	 	: in std_logic;
		delay1	: in std_logic;
		--clk		: in std_logic;
		h2wr	: out std_logic;
		h2rd 	: out std_logic;
		pulse 	: buffer std_logic
    );  
end conteol_cs_vhdl;

architecture v1 of conteol_cs_vhdl is
--signal pulse1 : std_logic ;
begin
	process(P27,hwr,hrd,pulse)--clk
    begin
	--if(clk'event and clk='1')then
		if (P27='0') then
			h2wr<=hwr; 
			h2rd<=hrd;
			pulse<='0';
		else --then
			if(pulse='0')then
				h2wr<='0';
				h2rd<='1';
				pulse<='1' and delay1;
			else --then
				h2wr<='1';
				h2rd<='1';
			end if;
		end if;
	--end if;
    end process;    
end v1;