8255_io_vhdl.txt

VHDL语言设计 8255并行I/O接口芯片

可编程8255并行I/O接口芯片设计：
VHDL源程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity PI8255A is
port(
reset,rd,wr,cs,a0,a1 : in std_ulogic;
pa                   : inout std_ulogic_vector(7 downto 0);
pb                   : inout std_ulogic_vector(7 downto 0);
pcl                  : inout std_ulogic_vector(3 downto 0);
pch                  : inout std_ulogic_vector(3 downto 0);
pd                   : inout std_ulogic_vector(7 downto 0);
      );
end PI8255A;

architecture rtl of PI8255A is
   signal internal_bus_out              :std_ulogic_vector(7 downto 0);
   signal internal_bus_in               :std_ulogic_vector(7 downto 0);
   signal st,ad,flag                    :std_ulogic_vector(1 downto 0);
   signal ctreg                         :std_ulogic_vector(7 downto 0);
   signal pa_latch,pb_latch,pc_latch    :std_ulogic_vector(7 downto 0);


begin


   p1:process(rd cs)

   begin;
 
     st<=ctrreg(3)&ctrreg(0)
     if(cs='0' and rd='0')then
          if(a0='0'and a1='0' and ctrreg(0)='1')then
                  internal_bus_in<=pa;
          elif(a0='1'and a1='0'and ctrreg(1)='0')then
                  internal_bus_in<=pb;
          elif(a0='0'and a1='1'and st="01")then
                  internal_bus_in(3 downto 0)<=pcl(3 downto 0);
          elif(a0='1'and a1='0'and ctrreg(1)='0')then
                  internal_bus_in(7 downto 4)<=pch(3 downto 0);
          elif(a0='1'and a1='0'and ctrreg(1)='0')then
                  internal_bus_in(3 downto 0)<=pcl(3 downto 0);
                  internal_bus_in(7 downto 4)<=pch(3 downto 0);
          end if;
     else
          internal_bus_in<="ZZZZZZZZ"
     end if;
          d<=inernal_bus_in;
   end process pl;


   p2 :process(cs,wr,reset)
      variable ctrregf        :std_ulogic;
      variable bctrreg_v      :ste_ulogic_vector(3 downto 0);
   begin
      if(cs='0' and wr='0')then
         ad<=a1&a0;
         ctrregf:=d(7);
         internal_bus_out<=d;
      end if;
      if(reset='1')then
         pa_latch<="00000000";
         pb_latch<="00000000";      
         pc_latch<="00000000"; 
         ctrreg  <="10011011";
         bctrreg_v :="0000"
         ctrregf   :='0';
      elsif(wr'event and wr='1')then
         if(ctrregf='1' and ad="11" and cs='0')then
             ctrreg<=internal_bus_out;
         elsif(ctrref='0' and cs='0' and ad="11")then
             bctrreg_v:=internal_bus_out(3 downto 0);
             case bctreeg_v is
                  when "0000"=>pc_latch(0)<='0';
                  when "0010"=>pc_latch(1)<='0';
                  when "0100"=>pc_latch(2)<='0';
                  when "0110"=>pc_latch(3)<='0';
                  when "1000"=>pc_latch(4)<='0';
                  when "1010"=>pc_latch(5)<='0';
                  when "1100"=>pc_latch(6)<='0';
                  when "1110"=>pc_latch(7)<='0';
                  when "0001"=>pc_latch(0)<='1';
                  when "0011"=>pc_latch(1)<='1';
                  when "0101"=>pc_latch(2)<='1';
                  when "0111"=>pc_latch(3)<='1';
                  when "1001"=>pc_latch(4)<='1';
                  when "1011"=>pc_latch(5)<='1';
                  when "1101"=>pc_latch(6)<='1';
                  when "1111"=>pc_latch(7)<='1';
                  when others=>flag<="11";
             end case;
          elsif(ctrreg(7)='1' and ad="00" and cs='0')then
              pa_latch>=internal_bus_out;
          elsif(ctrreg(7)='1' and ad="01" and cs='0')then
              pb_latch>=internal_bus_out;
          elsif(ctrreg(7)='1' and ad="10" and cs='0')then
              pc_latch>=internal_bus_out;
       
          end if;
    
       end if;
   end process;


   p3:process(pa_latch)
   begin
 
      if(ctrreg(1)='0')then
          pa<=pb_latch/
      else
          pa<="ZZZZZZZZ";
      end if;

    end process;


   p4:process(pb_latch)
   begin
   
      if(ctrreg(0)='0')then
          pb<=pb_latch;
      else
          pb<="ZZZZZZZZ";
      end if;
   end process;


   p5:process(pc_latch)
   begin
   
      if(ctrreg(0)='0')then
         pcl<=pc_latch(3 downto 0);
      else
         pcl<="ZZZZ";
      end if;
   end process;


   p6:process(pc_latch)
   begin
   
     if(ctrref(3)='0')then
        pch<=pc_latch(7 downto 4);
     else
        pch<="ZZZZ";
   end process;

end rtl;