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vhdl5.map.summary
Analysis & Synthesis Status : Successful - Thu Jan 03 01:29:42 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : vhdl5
Top-level Entity Name : vhdl5
Family : Strat
vhdl2.fit.rpt
Fitter report for Vhdl2
Thu Jan 03 00:04:58 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Fi
vhdl2.tan.rpt
Timing Analyzer report for Vhdl2
Thu Jan 03 00:05:03 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
vhdl2.fit.summary
Fitter Status : Successful - Thu Jan 03 00:04:58 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : Vhdl2
Top-level Entity Name : Vhdl2
Family : Stratix
Device : E
vhdl2.map.summary
Analysis & Synthesis Status : Successful - Thu Jan 03 00:04:46 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : Vhdl2
Top-level Entity Name : Vhdl2
Family : Strat
vhdl2.tan.summary
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Timing Analyzer Summary
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vhdl2.map.rpt
Analysis & Synthesis report for Vhdl2
Thu Jan 03 00:04:46 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal N
vhdl2.sim.vwf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
vhdl2.sim.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I