📄 vhdl2.tan.rpt
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Timing Analyzer report for Vhdl2
Thu Jan 03 00:05:03 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 9.176 ns ; G2B ; y[7] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1S10F484C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------+
; N/A ; None ; 9.176 ns ; G2B ; y[7] ;
; N/A ; None ; 9.174 ns ; G2B ; y[5] ;
; N/A ; None ; 9.161 ns ; G2B ; y[0] ;
; N/A ; None ; 9.159 ns ; G2B ; y[1] ;
; N/A ; None ; 9.116 ns ; G2B ; y[3] ;
; N/A ; None ; 9.101 ns ; G2B ; y[4] ;
; N/A ; None ; 9.095 ns ; G1 ; y[7] ;
; N/A ; None ; 9.093 ns ; G1 ; y[5] ;
; N/A ; None ; 9.080 ns ; G1 ; y[0] ;
; N/A ; None ; 9.078 ns ; G1 ; y[1] ;
; N/A ; None ; 9.035 ns ; G1 ; y[3] ;
; N/A ; None ; 9.020 ns ; G1 ; y[4] ;
; N/A ; None ; 8.928 ns ; d[1] ; y[5] ;
; N/A ; None ; 8.923 ns ; d[1] ; y[7] ;
; N/A ; None ; 8.912 ns ; d[1] ; y[0] ;
; N/A ; None ; 8.906 ns ; d[1] ; y[1] ;
; N/A ; None ; 8.867 ns ; d[1] ; y[4] ;
; N/A ; None ; 8.864 ns ; d[1] ; y[3] ;
; N/A ; None ; 8.840 ns ; d[0] ; y[5] ;
; N/A ; None ; 8.839 ns ; d[0] ; y[7] ;
; N/A ; None ; 8.824 ns ; d[0] ; y[0] ;
; N/A ; None ; 8.823 ns ; d[0] ; y[1] ;
; N/A ; None ; 8.781 ns ; d[0] ; y[3] ;
; N/A ; None ; 8.780 ns ; d[0] ; y[4] ;
; N/A ; None ; 8.744 ns ; G2B ; y[6] ;
; N/A ; None ; 8.710 ns ; d[2] ; y[7] ;
; N/A ; None ; 8.707 ns ; d[2] ; y[5] ;
; N/A ; None ; 8.694 ns ; d[2] ; y[0] ;
; N/A ; None ; 8.692 ns ; d[2] ; y[1] ;
; N/A ; None ; 8.663 ns ; G1 ; y[6] ;
; N/A ; None ; 8.650 ns ; d[2] ; y[3] ;
; N/A ; None ; 8.640 ns ; d[2] ; y[4] ;
; N/A ; None ; 8.502 ns ; d[1] ; y[2] ;
; N/A ; None ; 8.501 ns ; d[1] ; y[6] ;
; N/A ; None ; 8.497 ns ; G2A ; y[7] ;
; N/A ; None ; 8.495 ns ; G2A ; y[5] ;
; N/A ; None ; 8.487 ns ; G2B ; y[2] ;
; N/A ; None ; 8.482 ns ; G2A ; y[0] ;
; N/A ; None ; 8.480 ns ; G2A ; y[1] ;
; N/A ; None ; 8.437 ns ; G2A ; y[3] ;
; N/A ; None ; 8.422 ns ; G2A ; y[4] ;
; N/A ; None ; 8.416 ns ; d[0] ; y[2] ;
; N/A ; None ; 8.414 ns ; d[0] ; y[6] ;
; N/A ; None ; 8.406 ns ; G1 ; y[2] ;
; N/A ; None ; 8.276 ns ; d[2] ; y[6] ;
; N/A ; None ; 8.276 ns ; d[2] ; y[2] ;
; N/A ; None ; 8.065 ns ; G2A ; y[6] ;
; N/A ; None ; 7.808 ns ; G2A ; y[2] ;
+-------+-------------------+-----------------+------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Thu Jan 03 00:05:03 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Vhdl2 -c Vhdl2 --timing_analysis_only
Info: Longest tpd from source pin "G2B" to destination pin "y[7]" is 9.176 ns
Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_K17; Fanout = 1; PIN Node = 'G2B'
Info: 2: + IC(3.635 ns) + CELL(0.280 ns) = 5.149 ns; Loc. = LC_X1_Y22_N2; Fanout = 8; COMB Node = 'process0~78'
Info: 3: + IC(0.396 ns) + CELL(0.075 ns) = 5.620 ns; Loc. = LC_X1_Y22_N7; Fanout = 1; COMB Node = 'y~119'
Info: 4: + IC(1.180 ns) + CELL(2.376 ns) = 9.176 ns; Loc. = PIN_H17; Fanout = 0; PIN Node = 'y[7]'
Info: Total cell delay = 3.965 ns ( 43.21 % )
Info: Total interconnect delay = 5.211 ns ( 56.79 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Thu Jan 03 00:05:03 2008
Info: Elapsed time: 00:00:01
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