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__projnav.log
Project Navigator Auto-Make Log File
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Started process "Synthesize".
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*
hdllib.ref
AR djs behavioral F:/dragon/VHDL/myboard/JIAOTONG/DJS.vhdl sub00/vhpl01 1176292674
AR f05ms behavioral E:/VHDL/JIAOTONG/f05ms.vhdl sub00/vhpl24 0
EN f1s NULL F:/dragon/VHDL/myboard/JIAOTONG/f1s.vhdl
wed.zsf
E:/new vhdl/vhdl10/db/Vhdl10.sim.vwf 2935 36931 774 36648 0
E:/new vhdl/vhdl10/Vhdl10.vwf 37000 83250 20 1000 0
wed.zsf
E:/new vhdl/vhdl2/db/Vhdl2.sim.vwf 13136 78817 1071 65681 7
E:/new vhdl/vhdl2/Vhdl2.vwf 1325 93825 925 92500 0
vhdl1.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
wed.zsf
E:/new vhdl/Vhdl1/db/Vhdl1.sim.vwf 0 27950 20 1000 0
E:/new vhdl/Vhdl1/Vhdl1.vwf 0 1000000 20 1000 0
clk_2div.vhdl
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:41:47 03/11/2008
-- Design Name:
-- Module Name: clk_2div -