vhdl1.map.qmsg

程序提供了一种2选1选择器的算法

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 29 00:27:50 2007 " "Info: Processing started: Sat Dec 29 00:27:50 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Vhdl1 -c Vhdl1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Vhdl1 -c Vhdl1" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Vhdl1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Vhdl1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Vhdl1-choice " "Info: Found design unit 1: Vhdl1-choice" {  } { { "Vhdl1.vhd" "" { Text "E:/new vhdl/Vhdl1/Vhdl1.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 Vhdl1 " "Info: Found entity 1: Vhdl1" {  } { { "Vhdl1.vhd" "" { Text "E:/new vhdl/Vhdl1/Vhdl1.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Vhdl1 " "Info: Elaborating entity \"Vhdl1\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "a Vhdl1.vhd(13) " "Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(13): signal \"a\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Vhdl1.vhd" "" { Text "E:/new vhdl/Vhdl1/Vhdl1.vhd" 13 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "b Vhdl1.vhd(15) " "Warning (10492): VHDL Process Statement warning at Vhdl1.vhd(15): signal \"b\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Vhdl1.vhd" "" { Text "E:/new vhdl/Vhdl1/Vhdl1.vhd" 15 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "5 " "Info: Implemented 5 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "1 " "Info: Implemented 1 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 29 00:27:52 2007 " "Info: Processing ended: Sat Dec 29 00:27:52 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}