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Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file F:/dragon/VHDL/lzhu/song.vhdl in Library work.ERROR:HDLParsers:3312 - F:/dragon/VHDL/lzhu/song.vhdl Line 27. Undefined symbol 'clk'.ERROR:HDLParsers:1209 - F:/dragon/VHDL/lzhu/song.vhdl Line 27. clk: Undefined symbol (last report in this block)--> Total memory usage is 60744 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file F:/dragon/VHDL/lzhu/song.vhdl in Library work.Entity <song> (Architecture <Behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <song> (Architecture <Behavioral>).INFO:Xst:1739 - HDL ADVISOR - F:/dragon/VHDL/lzhu/song.vhdl line 13: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.WARNING:Xst:819 - F:/dragon/VHDL/lzhu/song.vhdl line 48: The following signals are missing in the process sensitivity list: counter.Entity <song> analyzed. Unit <song> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <song>. Related source file is F:/dragon/VHDL/lzhu/song.vhdl. Found 256x7-bit ROM for signal <digit>. Found 1-bit register for signal <speaker>. Found 1-bit register for signal <carrier>. Found 2-bit up counter for signal <count>. Found 8-bit up counter for signal <counter>. Found 13-bit up counter for signal <divider>. Summary: inferred 1 ROM(s). inferred 3 Counter(s). inferred 2 D-type flip-flop(s).Unit <song> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# ROMs : 1 256x7-bit ROM : 1# Counters : 3 13-bit up counter : 1 8-bit up counter : 1 2-bit up counter : 1# Registers : 2 1-bit register : 2==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <song> ...Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block song, actual ratio is 9.FlipFlop counter_3 has been replicated 1 time(s)FlipFlop counter_2 has been replicated 1 time(s)FlipFlop counter_1 has been replicated 1 time(s)FlipFlop counter_0 has been replicated 1 time(s)FlipFlop counter_4 has been replicated 1 time(s)FlipFlop counter_3 has been replicated 1 time(s)FlipFlop counter_2 has been replicated 1 time(s)=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s50tq144-6 Number of Slices: 74 out of 768 9% Number of Slice Flip Flops: 32 out of 1536 2% Number of 4 input LUTs: 124 out of 1536 8% Number of bonded IOBs: 13 out of 96 13% Number of GCLKs: 2 out of 4 50% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk4m | BUFGP | 14 |carrier:Q | NONE | 3 |clk4 | BUFGP | 15 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -6 Minimum period: 9.644ns (Maximum Frequency: 103.691MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 16.266ns Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Create Schematic Symbol".Compiling vhdl file F:/dragon/VHDL/lzhu/song.vhdl in Library work.Entity <song> (Architecture <behavioral>) compiled.tdtfi(vhdl) completed successfully.
Release 6.2i - spl2sym G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Create Schematic Symbol".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file F:/dragon/VHDL/lzhu/fpq4hz.vhdl in Library work.Entity <fpq4hz> (Architecture <Behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <fpq4hz> (Architecture <Behavioral>).Entity <fpq4hz> analyzed. Unit <fpq4hz> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <fpq4hz>. Related source file is F:/dragon/VHDL/lzhu/fpq4hz.vhdl. Found 1-bit tristate buffer for signal <CP>. Found 22-bit comparator lessequal for signal <$n0002>. Found 22-bit comparator greatequal for signal <$n0007>. Found 22-bit comparator lessequal for signal <$n0008>. Found 22-bit up counter for signal <a>. Found 1-bit register for signal <Mtridata_CP> created at line 28. Found 1-bit register for signal <Mtrien_CP> created at line 28. Summary: inferred 1 Counter(s). inferred 2 D-type flip-flop(s). inferred 3 Comparator(s). inferred 1 Tristate(s).Unit <fpq4hz> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Counters : 1 22-bit up counter : 1# Registers : 2 1-bit register : 2# Comparators : 3 22-bit comparator lessequal : 2 22-bit comparator greatequal : 1# Tristates : 1 1-bit tristate buffer : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <fpq4hz> ...Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block fpq4hz, actual ratio is 6.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s50tq144-6 Number of Slices: 61 out of 768 7% Number of Slice Flip Flops: 24 out of 1536 1% Number of 4 input LUTs: 97 out of 1536 6% Number of bonded IOBs: 1 out of 96 1% Number of GCLKs: 1 out of 4 25% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+CLK | BUFGP | 24 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -6 Minimum period: 9.451ns (Maximum Frequency: 105.809MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 6.927ns Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Create Schematic Symbol".Compiling vhdl file F:/dragon/VHDL/lzhu/fpq4hz.vhdl in Library work.Entity <fpq4hz> (Architecture <behavioral>) compiled.tdtfi(vhdl) completed successfully.
Release 6.2i - spl2sym G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Create Schematic Symbol".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file F:/dragon/VHDL/lzhu/fpq2_5.vhdl in Library work.ERROR:HDLParsers:1202 - F:/dragon/VHDL/lzhu/fpq2_5.vhdl Line 19. Redeclaration of symbol divide2.ERROR:HDLParsers:3312 - F:/dragon/VHDL/lzhu/fpq2_5.vhdl Line 27. Undefined symbol 'PRESET'.ERROR:HDLParsers:1209 - F:/dragon/VHDL/lzhu/fpq2_5.vhdl Line 27. PRESET: Undefined symbol (last report in this block)--> Total memory usage is 61000 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file F:/dragon/VHDL/lzhu/fpq2_5.vhdl in Library work.ERROR:HDLParsers:1202 - F:/dragon/VHDL/lzhu/fpq2_5.vhdl Line 19. Redeclaration of symbol divide2.--> Total memory usage is 60808 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".⌨️ 快捷键说明
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