fpq2_5.vhdl

来自「自己写的<<梁祝>>歌曲,主要改变歌谱,就可以实现任意的」· VHDL 代码 · 共 42 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity FPQ2_5 is
 PORT( INCLK:IN STD_LOGIC; ---时钟源
		 OUTCLK:BUFFER STD_LOGIC);
end FPQ2_5;

architecture Behavioral of FPQ2_5 is
 SIGNAL COUNT:STD_LOGIC_VECTOR(3 DOWNTO 0);
 SIGNAL CLK,clk1:STD_LOGIC;
  SIGNAL divide2:STD_LOGIC:='0';
begin
	 CLK<=INCLK XOR DIVIDE2;
	 CLK1<=CLK;
	 PROCESS(CLK)
	  BEGIN 
	   IF CLK'EVENT AND CLK='1' THEN
		  IF COUNT="0000" THEN
		    COUNT<="0010";
			 OUTCLK<='1';
			ELSE 
			 COUNT<=COUNT-1;
			 OUTCLK<='0';
			 END IF;
		  END IF;
	 END PROCESS;
	 PROCESS(OUTCLK)
	  BEGIN
	   IF OUTCLK'EVENT AND OUTCLK='1' THEN
		  DIVIDE2<=NOT DIVIDE2;
		  END IF;
		END PROCESS;
end Behavioral;