clk_2div.vhdl

vhdl语言编写的2分频器代码

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    11:41:47 03/11/2008 
-- Design Name: 
-- Module Name:    clk_2div - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clk_2div is
    Port ( clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           clk_2d : out  STD_LOGIC);
end clk_2div;

architecture Behavioral of clk_2div is
signal count:STD_LOGIC_VECTOR(3 DOWNTO 0);
begin
   process(clk)
	begin
	   if(rst='1')then
		   count<="0000";
	   elsif(clk'event and clk='1')then
		  if(count="1111")then
		     count<=(others=>'0');
		  else
		     count<=count+'1';
		  end if;
		end if;
	end process;
	clk_2d<=count(0);
end Behavioral;