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vhdl1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all; -----库文件
entity jianpan is
port(clk : in std_logic;
63_vhdl.vhd
-- Author : yzf
-- Created On: Fri Dec 8 09:35:16 1995
-- Testbench for gcd_disp.gcd_disp
library STD;
library WORK;
use STD.STANDARD.ALL;
use WORK.ALL;
entity test_gcd_disp is
end t
fpdiv_vhdl.txt
--
--
--------------------------------------------------------------------------------/
-- DESCRIPTION : Signed divider
-- A (A) input width : 4
-- B (B) inpu
multi_vhdl.txt
--
--------------------------------------------------------------------------------/
-- DESCRIPTION : Signed mulitplier:
-- A (A) input width : 4
-- B (B) inpu
cpu_16.vhdl
library IEEE;
library UNISIM;
use ieee.std_logic_1164.all;
use UNISIM.VComponents.all;
entity CPU_16 is
port(
clk: in std_logic;
RST: in std_logic;
Dbus: inout std_logic_vector(15 dow
write_back.vhdl
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use UNISIM.VComponents.all;
entity write_back is
port(
T4: in std_l
visit_memory.vhdl
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use UNISIM.VComponents.all;
entity visit_memory is
port(
PCload: in
vhdl1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity led1 is
port(ledin:in std_logic_vector(3 downto 0);
ledout:out std_logic_vector(6 downto 0));
end led