cpu_16.vhdl

16位cpu设计VHDL源码

library IEEE;
library UNISIM;
use ieee.std_logic_1164.all;
use UNISIM.VComponents.all;

entity CPU_16 is
	port(
		clk: in std_logic;
		RST: in std_logic;
		Dbus: inout std_logic_vector(15 downto 0);
		Abus: out std_logic_vector(15 downto 0);
		nWR: out std_logic;
		nRD: out std_logic;
		nBLE: out std_logic;
		nBHE: out std_logic;
		nMREQ: out std_logic);
end CPU_16;

architecture Behavioral of CPU_16 is
	component bufgp
		port(I: in std_logic; O: out std_logic);
	end component;

	component alu
		port(
		 	T2: in std_logic;
			T3: in std_logic;
			clk: in std_logic;
			Rupdate: in std_logic;
			Radd: in std_logic_vector(2 downto 0);
			Rdata: in std_logic_vector(7 downto 0);
			IRout: in std_logic_vector(15 downto 0);
			MRD_C: out std_logic;
			MWR_C: out std_logic;
			Addr: out std_logic_vector(15 downto 0);
			ALUout: out std_logic_vector(7 downto 0));
	end component;

	component clock
		port(
			clk: in std_logic;
			RST: in std_logic;
			T: out std_logic_vector(4 downto 0));
	end component;

	component code
		port(
			T0: in std_logic;
			T1: in std_logic;
			RST: in std_logic;
			clk: in std_logic;
			PCupdate: in std_logic;
			PCnew: in std_logic_vector(15 downto 0);
			IRnew: in std_logic_vector(15 downto 0);
			PCload: out std_logic;
			IRout: out std_logic_vector(15 downto 0);
			PCout: out std_logic_vector(15 downto 0));
	end component;

	component memory
		port(
			T3: in std_logic;
			MRD_C: in std_logic;
			MWR_C: in std_logic;
			Rtemp: out std_logic_vector(7 downto 0);
			data: in std_logic_vector(7 downto 0);
			nMRD: out std_logic;
			nMWR: out std_logic);
	end component;

	component visit_memory
		port(
			PCload: in std_logic;
			PCout: in std_logic_vector(15 downto 0);
			IRnew: out std_logic_vector(15 downto 0);
			clk: in std_logic;
			nMRD: in std_logic;
			nMWR: in std_logic;
			Addr: in std_logic_vector(15 downto 0);
			ALUout: in std_logic_vector(7 downto 0);
			data: out std_logic_vector(7 downto 0);
	
			Dbus: inout std_logic_vector(15 downto 0);
			Abus: out std_logic_vector(15 downto 0);
			nWR: out std_logic;
			nRD: out std_logic;
			nBLE: out std_logic;
			nBHE: out std_logic;
			nMREQ: out std_logic);
	end component;

	component write_back
		port(
			clk: in std_logic;
			T4: in std_logic;
			Rtemp: in std_logic_vector(7 downto 0);
			ALUout: in std_logic_vector(7 downto 0);
			Addr: in std_logic_vector(15 downto 0);
			IRout: in std_logic_vector(15 downto 0);
			Rupdate: out std_logic;
			PCupdate: out std_logic;
			Radd: out std_logic_vector(2 downto 0);
			Rdata: out std_logic_vector(7 downto 0);
			PCnew: out std_logic_vector(15 downto 0));
	end component;
	signal clkgp: std_logic;
	signal T_C: std_logic_vector(4 downto 0);
	signal Rupdate_C, PCload_C, PCupdate_C, nMRD_C, nMWR_C, MRD_C_C, MWR_C_C: std_logic;
	signal PCnew_C, IRnew_C, PCout_C, Addr_C, IRout_C: std_logic_vector(15 downto 0);
	signal Rdata_C, Rtemp_C, ALUout_C, data_C: std_logic_vector(7 downto 0);
	signal Radd_C: std_logic_vector(2 downto 0);
begin
   	u1: bufgp port map(I => clk, O => clkgp);
	u2: alu port map(
		T2 => T_C(2), 
		T3 => T_C(3),
		clk => clkgp, 
		Rupdate => Rupdate_C, 
		Radd => Radd_C, 
		Rdata => Rdata_C, 
		IRout => IRout_C, 
		MRD_C => MRD_C_C, 
		MWR_C => MWR_C_C, 
		Addr => Addr_C, 
		ALUout => ALUout_C);
	u3: clock port map(
		clk => clkgp, 
		RST => RST, 
		T => T_C);
	u4: code port map(
		T0 => T_C(0),
		T1 => T_C(1),   
		clk => clkgp, 
		RST => RST, 
		PCupdate => PCupdate_C, 
		PCnew => PCnew_C, 
		IRnew => IRnew_C, 
		PCload => PCload_C, 
		IRout => IRout_C, 
		PCout => PCout_C);
	u5: memory port map(
		T3 => T_C(3),
		MRD_C => MRD_C_C, 
		MWR_C => MWR_C_C, 
		Rtemp => Rtemp_C, 
		data => data_C, 
		nMRD => nMRD_C, 
		nMWR => nMWR_C);
	u6: visit_memory port map(
		clk => clkgp, 
		PCload => PCload_C, 
		PCout => PCout_C, 
		IRnew => IRnew_C, 
		nMRD => nMRD_C, 
		nMWR => nMWR_C, 
		Addr => Addr_C, 
		ALUout => ALUout_C, 
		data => data_C, 
		Dbus => Dbus, 
		Abus => Abus, 
		nWR => nWR, 
		nRD => nRD, 
		nBLE => nBLE, 
		nBHE => nBHE, 
		nMREQ => nMREQ);
	u7: write_back port map(
		T4 => T_C(4), 
		clk => clkgp, 
		Rtemp => Rtemp_C, 
		ALUout => ALUout_C, 
		Addr => Addr_C, 
		IRout => IRout_C,
		Rupdate => Rupdate_C, 
		PCupdate => PCupdate_C, 
		Radd => Radd_C, 
		Rdata => Rdata_C, 
		PCnew => PCnew_C);
end Behavioral;