write_back.vhdl

16位cpu设计VHDL源码

library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use UNISIM.VComponents.all;

entity write_back is
port(
	T4: in std_logic;
	clk: in std_logic;
	Rtemp: in std_logic_vector(7 downto 0);
	ALUout: in std_logic_vector(7 downto 0);
	Addr: in std_logic_vector(15 downto 0);
	IRout: in std_logic_vector(15 downto 0);
	Rupdate: out std_logic;
	PCupdate: out std_logic;
	Radd: out std_logic_vector(2 downto 0);
	Rdata: out std_logic_vector(7 downto 0);
	PCnew: out std_logic_vector(15 downto 0));
end write_back;

architecture Behavioral of write_back is
component bufgp
	port(I: in std_logic; O: out std_logic);
end component;
signal clkgp: std_logic;
begin
	u1: bufgp port map(I => clk, O => clkgp);
	process(IRout, T4)
	begin
		Rupdate <= '0';
		PCupdate <= '0';
		Radd <= "ZZZ";
		Rdata <= (others => 'Z');
		PCnew <= (others => 'Z');
		if(T4 = '1' and IRout(15) = '1') then
			PCnew <= Addr; 
			if(ALUout = "00000000" and IRout(12) = '0') then --JZ
				PCupdate <= '1';
			elsif(IRout(12) = '1') then --JMP
				PCupdate <= '1';
			end if;
		elsif(T4 = '1' and IRout(15) = '0') then
			case IRout(14 downto 12) is
				when "111" => --LDA
					Rdata <= Rtemp;
					Rupdate <= '1';
					Radd <= IRout(10 downto 8);
				when "110" => NULL;	--STA
				when others => 
					Rdata <= ALUout;
					Rupdate <= '1';
					Radd <= IRout(10 downto 8);
			end case;
		end if;
	end process;
end Behavioral;