visit_memory.vhdl

16位cpu设计VHDL源码

library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use UNISIM.VComponents.all;

entity visit_memory is
port(
	PCload: in std_logic;
	PCout: in std_logic_vector(15 downto 0);
	IRnew: out std_logic_vector(15 downto 0);
	clk: in std_logic;
	nMRD: in std_logic;
	nMWR: in std_logic;
	Addr: in std_logic_vector(15 downto 0);
	ALUout: in std_logic_vector(7 downto 0);
	data: out std_logic_vector(7 downto 0);
	Dbus: inout std_logic_vector(15 downto 0);
	Abus: out std_logic_vector(15 downto 0);
	nWR: out std_logic;
	nRD: out std_logic;
	nBLE: out std_logic;
	nBHE: out std_logic;
	nMREQ: out std_logic);
end visit_memory;

architecture Behavioral of visit_memory is
component bufgp
	port(I: in std_logic; O: out std_logic);
end component;
signal clkgp: std_logic;
begin
	u1: bufgp port map(I => clk, O => clkgp);
	process(PCload, nMWR, nMRD, clkgp)
	begin
		Dbus <= (others => 'Z');
		Abus <= (others => 'Z');
		nRD <= '1';
		nWR <= '1';
		nBLE <= '1';
		nBHE <= '1';
		nMREQ <= '1';
		if(PCload = '1') then --ȡָ
			Abus <= PCout;
			nRD <= '0';
			nWR <= '1';
			nMREQ <= '0';
			nBLE <= '0';
			nBHE <= '0';
			IRnew <= Dbus;
		elsif(nMWR = '0') then --STA
			Abus <= Addr;
			nMREQ <= '0';
			nBLE <= '0';
			nBHE <= '1';
			nWR <= '0';
			nRD <= '1';
			Dbus(7 downto 0) <= ALUout;
		elsif(nMRD = '0') then --LDA
			Abus <= Addr;
			nMREQ <= '0';
			nBLE <= '0';
			nBHE <= '1';
			nRD <= '0';
			nWR <= '1';
			data <= Dbus(7 downto 0);
		else
			Dbus <= (others => 'Z');
		end if;
	end process;
end Behavioral;