代码搜索结果
找到约 10,000 项符合
VHDL 的代码
three-vhdl.txt
分频的VHDL程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY Odd_Fren is
port(Clk : in std_logic;
O : out std_logic);
end Odd_Fren;
architecture bev
vhdl1.vhd
-- Quartus VHDL Template
-- State Machine with Asynchronous Reset (1 block)
-- State Machine outputs will be registered
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY vhdl1 IS
PORT
(
ethernet_vhdl.ucf
NET "clk" LOC = "B14" ;
NET "phy_rst" LOC="K1";
NET "board_reset" LOC ="AA23" ;
##--------------GMII----------------
NET "gmii_rxd" LOC = "H1" ;
NET "gmii_rxd" LOC = "K4" ;
NET
ethernet_vhdl.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity ethernet is
Port ( clk,board
led_vhdl.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity lcd is
Port ( clk,reset
vga_vhdl.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity vga is
Port ( reset_display
lifang_vhdl.txt
发信人: AnalogIC (类比积体电路), 信区: METech
标 题: y=x^(1/3)的VHDL实现(Modelsim 仿真 DC综合通过)
发信站: BBS 水木清华站 (Tue Aug 20 17:04:10 2002), 转信
--IME Tsinghua University
--Author : AnalogIC
--2002-8-20
--I