lifang_vhdl.txt

该代码是实现函数的立方源代码

发信人: AnalogIC (类比积体电路), 信区: METech       
标  题: y=x^(1/3)的VHDL实现(Modelsim 仿真 DC综合通过)
发信站: BBS 水木清华站 (Tue Aug 20 17:04:10 2002), 转信

--IME Tsinghua University
--Author : AnalogIC
--2002-8-20
--It will take eleven clock periods to get the result.
--If synthesized properly,it needs only once multiplication each clock period.
--cube_root.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity cube_root is
  port(x : in std_logic_vector(31 downto 0);
       y : out std_logic_vector(10 downto 0);
       done : out std_logic; -- indicate output y is ready
       clk : in std_logic;
       rdy : in std_logic); -- indicate input x is ready
end cube_root;
architecture cube of cube_root is

     signal root : std_logic_vector(10 downto 0);
     signal shifter : std_logic_vector(61 downto 0);
     signal counter : std_logic_vector(3 downto 0);
     signal diff : std_logic_vector(31 downto 0);
     signal prod : std_logic_vector(24 downto 0);
begin
      diff <= shifter(61 downto 30) - prod;
      done <= '1' when counter="0000" else
              '0';
      y <= root;
      process
      begin
         wait until clk'event and clk='1';
         if (rdy='1') then
             root <= (others=>'0');
             shifter(31 downto 0) <= x;
             shifter(61 downto 32) <= (others=>'0');
             counter <= "1011";
         else
             case diff(31) is
             when '1' => shifter(61 downto 33) <= shifter(58 downto 30);
             when others => shifter(61 downto 33) <=diff(28 downto 0);
             end case;
             shifter(32 downto 3) <=shifter(29 downto 0);
             shifter(2 downto 0) <="000";
             root(10 downto 1) <= root(9 downto 0);
             root(0) <= not (diff(31));
             counter <= counter - '1';
         end if;
      end process;

      process (root)
      --variable twice_root : std_logic_vector(11 downto 0);
      variable mid_prod : std_logic_vector(23 downto 0);
      begin
         --twice_root := root & '0';
         mid_prod :=(root & '0')* (root & '1');
         prod <= (mid_prod & '1')+ mid_prod;
      end process;
end cube;
--------------------------------------------------------------------
--tb_cube_root.vhd
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity tb_cube_root is
end tb_cube_root;
architecture tb_design of tb_cube_root is
component cube_root
     port(x : in std_logic_vector(31 downto 0);
          y : out std_logic_vector(10 downto 0);
          done : out std_logic;
          clk : in std_logic;
          rdy : in std_logic);
end component;
signal x_wire : std_logic_vector(31 downto 0) :=to_stdlogicvector(X"0000_000
0");
signal y_wire : std_logic_vector(10 downto 0);
signal done_wire : std_logic;
signal clk_wire : std_logic := '0';
signal rdy_wire : std_logic := '0';
begin
   UUT : cube_root
         port map (x => x_wire,
                   y => y_wire,
                   done => done_wire,
                   clk  => clk_wire,
                   rdy => rdy_wire);
   clk_wire <= not (clk_wire) after 10 ns;
   process
   begin
      wait for 5 ns;
      rdy_wire <= '1';
      x_wire(31 downto 0) <= to_stdlogicvector(X"FDFD_DFDF");
      wait for 15 ns;
      rdy_wire <= '0';
      x_wire <= to_stdlogicvector(X"0000_0000");
      wait until done_wire = '1';
      wait for 20 ns;
   end process;
end tb_design;

----------------------------------------------------------------
---run this test bench 240 ns 
---result for this testbench is
---y = "11001010101"
----------------------------------------------------------------

  Analog circuit designers tend to think of themselves as
lone cowboys, brave pioneers, creative and independent types,
in contrast to the herd animals of the digital IC world.