📄 vga_vhdl.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity vga is
Port ( reset_display : in std_logic; video_clk, test_clk : out std_logic; vga_hsyncb,vga_vsyncb : out std_logic; dvd_psave, vga_blank, vga_csync : out std_logic;
red,gre,blu: out std_logic_vector(7 downto 0) );
end vga;
architecture vga_arch of vga is
signal cnt,cnt_div : std_logic_vector(1 downto 0); -- user pixel countersignal hcnt : std_logic_vector(8 downto 0); -- horizontal pixel countersignal vcnt : std_logic_vector(9 downto 0); -- vertical line countersignal pixrg : std_logic_vector(7 downto 0); -- byte-wide register for 4 pixelssignal clock : std_logic;signal hsyncb: std_logic; -- horizontal (line) syncsignal vsyncb: std_logic; -- vertical (frame) sync signal blank : std_logic; -- video blanking signalsignal pblank: std_logic; -- pipelined video blanking signal
signal reset : std_logic;
begin
vga_hsyncb <= hsyncb; vga_vsyncb <= vsyncb; dvd_psave <= '1' ; vga_csync <= '0' ; vga_blank <= '1' ; clock <= cnt_div(1); video_clk <= cnt_div(1);
vga_rst : process(clock,reset_display) begin if reset_display='1' then cnt <= "00"; elsif (clock'event and clock='1') then cnt <= cnt + 1; end if;end process;vga_div: process(clk,reset_display) begin if reset_display='1' then cnt_div <= "00"; elsif (clk'event and clk ='1') then cnt_div <= cnt_div + 1; end if;end process; A: process(clock,reset_display) begin if reset_display='1' then hcnt <= "000000000"; elsif (clock'event and clock='1') then -- horiz. pixel counter rolls-over after 381 pixels if hcnt<380 then hcnt <= hcnt + 1; else hcnt <= "000000000"; end if; end if;end process;B: process(hsyncb,reset_display) begin if reset_display='1' then vcnt <= "0000000000"; elsif (hsyncb'event and hsyncb='1') then -- vert. line counter rolls-over after 528 lines if vcnt<527 then vcnt <= vcnt + 1; else vcnt <= "0000000000"; end if; end if;end process;C: process(clock,reset_display)begin if reset_display='1' then hsyncb <= '1'; elsif (clock'event and clock='1') then -- horiz. sync is low in this interval to signal start of a new line if (hcnt>=291 and hcnt<337) then hsyncb <= '0'; else hsyncb <= '1'; end if; end if;end process;D: process(hsyncb,reset_display) begin if reset_display='1' then vsyncb <= '1'; elsif (hsyncb'event and hsyncb='1') then -- vert. sync is low in this interval to signal start of a new frame if (vcnt>=490 and vcnt<492) then vsyncb <= '0'; else vsyncb <= '1'; end if; end if;end process;-- blank video outside of visible region: (0,0) -> (255,479)E: blank <= '1' when (hcnt>=256 or vcnt>=480) else '0';-- store the blanking signal for use in the next pipeline stageF: process(clock,reset_display) begin if reset_display='1' then pblank <= '0'; elsif (clock'event and clock='1') then pblank <= blank; end if;end process;-- the color mapper translates each 2-bit pixel into a 6-bit-- color value. When the video signal is blanked, the color-- is forced to zero (black).J: process(clock,reset_display)begin -- blank the video on reset if reset_display='1' then red <= "00000000"; gre <= "00000000"; blu <= "00000000"; -- update the color outputs on every dot clock elsif (clock'event and clock='1') then -- map the pixel to a color if the video is not blanked if pblank='0' then case cnt is when "00" => red <= "11110000"; gre <= "00000000"; blu <= "00000000"; when "01" => red <= "00000000"; gre <= "11110000"; blu <= "00000000"; when "10" => red <= "00000000"; gre <= "00000000"; blu <= "11110000"; when others => red <= "11111111"; gre <= "11111111"; blu <= "11111111"; -- white end case; -- otherwise, output black if the video is blanked else red <= "00000000"; gre <= "00000000"; blu <= "00000000"; -- black end if; end if;end process;end vga_arch;
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