ethernet_vhdl.vhd

千兆以太网控制器.可以调整FIFO,和传输速率,在码流层进行控制.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity ethernet is
    Port ( clk,board_reset : in std_logic;
	 
           gmii_rxd    : in std_logic_vector(7 downto 0);
           gmii_rx_dv  : in std_logic;
           gmii_rx_clk : in std_logic;
			  
           gmii_txd    : out std_logic_vector(7 downto 0);
           gmii_tx_en  : out std_logic;
           gmii_tx_er  : out std_logic;
           gmii_tx_clk : out std_logic;
			  phy_rst 	  : out std_logic );
end ethernet;

architecture ethernet_arch of ethernet is

component infifo
	port (
	din: IN std_logic_VECTOR(7 downto 0);
	wr_en: IN std_logic;
	wr_clk: IN std_logic;
	rd_en: IN std_logic;
	rd_clk: IN std_logic;
	ainit: IN std_logic;
	dout: OUT std_logic_VECTOR(7 downto 0);
	full: OUT std_logic;
	empty: OUT std_logic);
END component;

COMPONENT ddcm
	PORT(
		CLKIN_IN : IN std_logic;
		RST_IN : IN std_logic;          
		CLKIN_IBUFG_OUT : OUT std_logic;
		CLK0_OUT : OUT std_logic;
		CLK90_OUT : OUT std_logic;
		CLK180_OUT : OUT std_logic;
		CLK270_OUT : OUT std_logic;
		LOCKED_OUT : OUT std_logic
		);
	END COMPONENT;

signal reset        :   std_logic;
signal locked       :	std_logic;
signal infifo_empty :	std_logic;
signal infifo_rd    :	std_logic;
signal infifo_dataout :	std_logic_vector(7 downto 0);

signal gmii_rx_dv_dly :	std_logic;
signal infifo_rd_dly  :	std_logic;
signal infifo_wr      :	std_logic;
signal infifo_datain :	std_logic_vector(7 downto 0);

signal infifo_wr_clk   :	std_logic;
signal infifo_wr_clk_n :	std_logic;

begin

phy_rst    <= '1';
gmii_tx_er <= '0';

box: infifo
	port map(
	din=> infifo_datain,
	wr_en=> infifo_wr,
	wr_clk=> infifo_wr_clk,
	rd_en=>infifo_rd ,
	rd_clk=> infifo_wr_clk,
	ainit=> reset,
	dout=> infifo_dataout,
	full=> open,
	empty=> infifo_empty
	);

Inst_ddcm: ddcm PORT MAP(
		CLKIN_IN => gmii_rx_clk,
		RST_IN => board_reset,
		CLKIN_IBUFG_OUT => open,
		CLK0_OUT => open,
		CLK90_OUT => open,
		CLK180_OUT => infifo_wr_clk,
		CLK270_OUT => open,
		LOCKED_OUT => locked
	);

reset<=not locked;


-------------recieve package to infifo-------------
process(reset,infifo_wr_clk)
	begin
		if reset='1' then
			infifo_datain<=(others=>'0');
		elsif infifo_wr_clk' event and infifo_wr_clk='1' then
			if (gmii_rx_dv='1') then
				infifo_datain<=gmii_rxd;
			end if;
		end if;
	end process;

process(reset,infifo_wr_clk)
	begin
		if reset='1' then
			infifo_wr<='0';
		elsif infifo_wr_clk' event and infifo_wr_clk='1' then
			infifo_wr<=gmii_rx_dv;
		end if;
	end process;

-------------translate package to infifo-------------
infifo_rd<=not infifo_empty;

process(reset,infifo_wr_clk)
	begin
		if reset='1' then
			infifo_rd_dly<='0';
		elsif infifo_wr_clk' event and infifo_wr_clk='1' then
			infifo_rd_dly<=infifo_rd;
		end if;
	end process;

process(reset,infifo_wr_clk)
	begin
		if reset='1' then
			gmii_tx_en<='0';
		elsif infifo_wr_clk' event and infifo_wr_clk='1' then
			gmii_tx_en<=infifo_rd_dly;
		end if;
	end process;

process(reset,infifo_wr_clk)
	begin
		if reset='1' then
			gmii_txd<=(others=>'0');
		elsif infifo_wr_clk' event and infifo_wr_clk='1' then
			gmii_txd<=infifo_dataout;
		end if;
	end process;

infifo_wr_clk_n<=not infifo_wr_clk;

OFDDRRSE_inst : OFDDRRSE
port map (
		Q => gmii_tx_clk, 
		C0 => infifo_wr_clk, 
		C1 => infifo_wr_clk_n, 
		CE => '1', 
		D0 => '1', 
		D1 => '0', 
		R => '0', 
		S => '0' 
		);

end ethernet_arch;