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VHDL 的代码
vhdl.vhd
-- generated by newgenasym Fri Mar 16 11:23:04 2001
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity CAP is
port (
A: INOUT STD_LOGIC;
B: INOUT
vhdl.vhd
-- generated by newgenasym Fri Mar 16 12:55:13 2001
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity PHOTO_DIODE is
port (
ANODE: INOUT STD_LOGIC;
CATHODE:
vhdl.vhd
-- generated by newgenasym Tue Mar 20 14:39:52 2001
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity DATA is
port (
GAIN: IN std_logic;
OUTA: OUT
vhdl.vhd
-- generated by newgenasym Thu Mar 22 13:53:53 2001
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity DAAMP is
port (
DQ0: IN std_logic;
DQ1: IN
vhdl.vhd
-- generated by newgenasym Thu May 10 13:22:43 2001
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity HIGH_SPEED_RAM is
port (
RA: IN std_logic_vector (15 DO
vhdl.vim
" Vim syntax file
" Language: VHDL
" Maintainer: Czo
" Credits: Stephan Hegel
" $Id: vhdl.vim,v 1.1.1.1 2001/06/07 21:35:13 corinna Exp $
"
vhdl.api
abs
access
add
after
alias
all
and
architecture
array
assert
attribute
begin
block
body
buffer
bus
case
component
configuration
constant
downto
else
elsif
end
entity
error
ex
vhdl.cpp
/*
*
LA-CC 05-135 Trident 0.7.1
Copyright Notice
Copyright 2006 (c) the Regents of the University of California.
This Software was produced under a U.S. Government contract
(W-7405-ENG-36) by Los
vhdl.txt
Keywords
Operators
Attributes
Standard Functions
Standard Packages
Standard Types
User Words