vhdl.vhd

cadence公司pcb内部培训的资料,并且附带其中的例子程序!比市面上任何一本cadence的书好!

-- generated by newgenasym Tue Mar 20 14:39:52 2001

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity DATA is
    port (    
	GAIN:      IN     std_logic;    
	OUTA:      OUT    std_logic;    
	OUTB:      OUT    std_logic;    
	VCLKA:     IN     std_logic;    
	VCLKC:     IN     std_logic;    
	VD:        IN     std_logic_vector (7 DOWNTO 0));
end DATA;