vhdl.vhd

cadence公司pcb内部培训的资料,并且附带其中的例子程序!比市面上任何一本cadence的书好!

-- generated by newgenasym Thu May 10 13:22:43 2001

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity HIGH_SPEED_RAM is
    port (    
	RA:        IN     std_logic_vector (15 DOWNTO 0);    
	RCS0:      IN     std_logic;    
	RCS1:      IN     std_logic;    
	RCS2:      IN     std_logic;    
	RCS3:      IN     std_logic;    
	RD:        OUT    std_logic_vector (7 DOWNTO 0);    
	RWE:       IN     std_logic);
end HIGH_SPEED_RAM;