vhdl.vhd

cadence公司pcb内部培训的资料,并且附带其中的例子程序!比市面上任何一本cadence的书好!

-- generated by newgenasym Thu Mar 22 13:53:53 2001

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity DAAMP is
    port (    
	DQ0:       IN     std_logic;    
	DQ1:       IN     std_logic;    
	DQ2:       IN     std_logic;    
	DQ3:       IN     std_logic;    
	DQ4:       IN     std_logic;    
	DQ5:       IN     std_logic;    
	DQ6:       IN     std_logic;    
	DQ7:       IN     std_logic;    
	GAIN:      IN     std_logic;    
	\out\:     OUT    std_logic;    
	VCLK:      IN     std_logic;    
	VREF:      IN     std_logic);
end DAAMP;