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VERSION 6 BEGIN SCHEMATIC BEGIN ATTR DeviceFamilyName "xc9500xl" DELETE all:0 EDITNAME all:0 EDITTRAIT all:0 END ATTR BEGIN NETLIST SIGNAL RST

VERSION 6 BEGIN SCHEMATIC BEGIN ATTR DeviceFamilyName "xc9500xl" DELETE all:0 EDITNAME all:0 EDITTRAIT all:0 END ATTR BEGIN NETLIST SIGNAL RST

# Schematic : PDCL (jhdparse) __projnav/top_jhdparse_tcl.rsp # Schematic : PDCL (jhdparse) __projnav/top_jhdparse_tcl.rsp # VHDL : Create Schematic Symbol __projnav/tb.rsp adecode.spl __projnav

VERSION 6 BEGIN SCHEMATIC BEGIN ATTR DeviceFamilyName "xc9500xl" DELETE all:0 EDITNAME all:0 EDITTRAIT all:0 END ATTR BEGIN NETLIST SIGNAL RST

# Schematic : PDCL (jhdparse) __projnav/top_jhdparse_tcl.rsp # Schematic : PDCL (jhdparse) __projnav/top_jhdparse_tcl.rsp # VHDL : Create Schematic Symbol __projnav/tb.rsp adecode.spl __projnav

(ExpressProject "" (ProjectVersion "19981106") (ProjectType "PCB") (Folder "Design Resources" (Folder "Library") (File ".\2000-11.dsn" (Type "Schematic Design")) (BuildF

# XST (Creating Lso File) : sreg8.lso # xst flow : RunXST sreg8.syr sreg8.prj sreg8.sprj sreg8.ana sreg8.stx sreg8.cmd_log sreg8.ngc sreg8.ngr # View RTL Schematic sreg8.ngr # XST (Creat

Protel Advanced Schematic Annotation Report for 'Sheet1.Sch' 17:43:44 12-Mar-2004 C? => C8 C? => C9 C? => C10 C? => C11

Protel Advanced Schematic Annotation Report for 'Sheet1.Sch' 17:43:44 12-Mar-2004 C? => C8 C? => C9 C? => C10 C? => C11

# Verilog : Create Schematic Symbol div16.spl __projnav/jhdparse.log # Verilog : Create Schematic Symbol div_256.spl __projnav/jhdparse.log # Verilog : Create Schematic Symbol ps2_keyboard_inte