videogenerator.prf

用lattice XP3 demo板设计的VGA信号发生器

SCHEMATIC START ;
# map:  version ispLever_v61_PROD_Build (37) -- WARNING: Map write only section -- Sat Jun 16 17:34:44 2007

SYSCONFIG PERSISTENT=OFF CONFIG_MODE=JTAG DONE_OD=ON DONE_EX=OFF MCCLK_FREQ=2.5 CONFIG_SECURE=OFF WAKE_UP=21 WAKE_ON_LOCK=OFF INBUF=ON ;
LOCATE COMP "UARTtx" SITE "102" ;
LOCATE COMP "clk" SITE "20" ;
LOCATE COMP "NUMdata_7" SITE "196" ;
LOCATE COMP "NUMdata_6" SITE "203" ;
LOCATE COMP "NUMdata_5" SITE "201" ;
LOCATE COMP "NUMdata_4" SITE "198" ;
LOCATE COMP "NUMdata_3" SITE "197" ;
LOCATE COMP "NUMdata_2" SITE "195" ;
LOCATE COMP "NUMdata_1" SITE "200" ;
LOCATE COMP "NUMdata_0" SITE "202" ;
LOCATE COMP "NUMlocation_3" SITE "193" ;
LOCATE COMP "NUMlocation_2" SITE "190" ;
LOCATE COMP "NUMlocation_1" SITE "191" ;
LOCATE COMP "NUMlocation_0" SITE "192" ;
LOCATE COMP "VGAdena" SITE "65" ;
LOCATE COMP "VGAv" SITE "62" ;
LOCATE COMP "VGAh_cs" SITE "61" ;
LOCATE COMP "VGAb_1" SITE "54" ;
LOCATE COMP "VGAb_0" SITE "55" ;
LOCATE COMP "VGAg_1" SITE "57" ;
LOCATE COMP "VGAg_0" SITE "56" ;
LOCATE COMP "VGAr_1" SITE "58" ;
LOCATE COMP "VGAr_0" SITE "60" ;
SCHEMATIC END ;
COMMERCIAL ;
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;

// No timing preferences found. TRCE invokes auto-generation of timing preferences
// Section Autogen
FREQUENCY PORT "clk"  86.866 MHz ;
FREQUENCY NET "clk_c"  86.866 MHz ;
// End Section Autogen