📄 uart_v.prf
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SCHEMATIC START ;
# map: version ispLever_v61_PROD_Build (37) -- WARNING: Map write only section -- Tue Jul 17 10:48:28 2007
SYSCONFIG PERSISTENT=OFF CONFIG_MODE=JTAG DONE_OD=ON DONE_EX=OFF MCCLK_FREQ=2.5 CONFIG_SECURE=OFF WAKE_UP=21 WAKE_ON_LOCK=OFF INBUF=ON ;
SCHEMATIC END ;
COMMERCIAL ;
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
// No timing preferences found. TRCE invokes auto-generation of timing preferences
// Section Autogen
FREQUENCY PORT "clk16x" 177.054 MHz ;
FREQUENCY NET "u1_clkdiv_3" 360.750 MHz ;
FREQUENCY NET "clk16x_c" 364.564 MHz ;
FREQUENCY NET "u2/clkdivZ0Z_3" 177.054 MHz ;
// End Section Autogen
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