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example_en_16bit_s.vhd
-- VHDL Model Created from SCS Schematic example_en_16bit_s.sch
-- Aug 14, 2003 12:15
-- Automatically generated by vdvhdl version 9.5 Release Build2
library IEEE;
use IEEE.std_logic_1164.a
example_en_4bit.vhd
-- VHDL Model Created from SCS Schematic example_en_4bit.sch
-- Aug 13, 2003 12:31
-- Automatically generated by vdvhdl version 9.5 Release Build2
library IEEE;
use IEEE.std_logic_1164.all;
example_en_4bit.v
/* Verilog Model Created from SCS Schematic example_en_4bit.sch
Aug 13, 2003 12:30 */
/* Automatically generated by hvveri version 9.5 Release Build2 */
`timescale 1ns/1ns
`define LOGIC
example_en_24bit_s.vhd
-- VHDL Model Created from SCS Schematic example_en_24bit_s.sch
-- Aug 14, 2003 16:14
-- Automatically generated by vdvhdl version 9.5 Release Build2
library IEEE;
use IEEE.std_logic_1164.a
lisa1.sdf
ISIS SCHEMATIC DESCRIPTION FORMAT 6.1
=====================================
Design: E:\zhou\模拟比赛\相关资料\PWM资料\P0口产生PWM信号\PWM.DSN
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Author:
Created: 09/0
lisa1.sdf
ISIS SCHEMATIC DESCRIPTION FORMAT 6.1
=====================================
Design: D:\awork\lx\proteus\DA\DAC0808\正弦波\DAC0808ls373正弦波.DSN
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Cr
sap1.adf
[Project]
Current Flow=Generic
VCS=0
version=1
modified=9
Current Config=compile
[Configurations]
compile=sap1
[Library]
sap1=.\sap1.LIB
[$LibMap$]
sap1=.
[Settings]
FLOW_TYPE=Schematic
alarmclk.vhd
-- VHDL model created from schematic alarmclk.sch -- Dec 15 15:08:40 2000
LIBRARY vanmacro;
USE vanmacro.components.ALL;
LIBRARY ieee;
LIBRARY generics;
USE ieee.std_logic_1164.ALL;
USE ieee.n
alarmclk.syn
JDF B
// Created by Version 9.0
PROJECT Demo
DESIGN alarmclk Normal
DEVKIT ispLSI5384VE-80LF256I
ENTRY ABEL/Schematic
STIMULUS test.abv
STIMULUS alarmclk.wdl
DOCUMENT spec.txt
MODULE alarmcl
lisa1.sdf
ISIS SCHEMATIC DESCRIPTION FORMAT 6.1
=====================================
Design: D:\a-51新书\book\ex4\ex4-2\ex4-2.DSN
Doc. no.:
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Author:
Created: 06/01/20
Mo