📄 example_en_24bit_s.vhd
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-- VHDL Model Created from SCS Schematic example_en_24bit_s.sch
-- Aug 14, 2003 16:14
-- Automatically generated by vdvhdl version 9.5 Release Build2
library IEEE;
use IEEE.std_logic_1164.all;
entity COUNTER_EN_4BIT_S is
Port ( clear : In STD_LOGIC;
clk : In STD_LOGIC;
enable : In STD_LOGIC;
qa_r : Out STD_LOGIC;
qb_r : Out STD_LOGIC;
qc_r : Out STD_LOGIC;
qd_r : Out STD_LOGIC );
end COUNTER_EN_4BIT_S;
architecture SCHEMATIC of COUNTER_EN_4BIT_S is
attribute syn_macro : integer;
attribute syn_macro of SCHEMATIC : architecture is 1;
signal BCD_a : STD_LOGIC;
signal ABCDE_a : STD_LOGIC;
signal ED_a : STD_LOGIC;
constant GND : STD_LOGIC := '0';
constant VCC : STD_LOGIC := '1';
signal qa_r_DUMMY : STD_LOGIC;
signal qb_r_DUMMY : STD_LOGIC;
signal qc_r_DUMMY : STD_LOGIC;
signal qd_r_DUMMY : STD_LOGIC;
component SUPER_LOGIC
Port ( A1 : In STD_LOGIC;
A2 : In STD_LOGIC;
A3 : In STD_LOGIC;
A4 : In STD_LOGIC;
A5 : In STD_LOGIC;
A6 : In STD_LOGIC;
B1 : In STD_LOGIC;
B2 : In STD_LOGIC;
C1 : In STD_LOGIC;
C2 : In STD_LOGIC;
D1 : In STD_LOGIC;
D2 : In STD_LOGIC;
E1 : In STD_LOGIC;
E2 : In STD_LOGIC;
F1 : In STD_LOGIC;
F2 : In STD_LOGIC;
F3 : In STD_LOGIC;
F4 : In STD_LOGIC;
F5 : In STD_LOGIC;
F6 : In STD_LOGIC;
MP : In STD_LOGIC;
MS : In STD_LOGIC;
NP : In STD_LOGIC;
\NS\ : In STD_LOGIC;
OP : In STD_LOGIC;
OS : In STD_LOGIC;
PP : In STD_LOGIC;
PS : In STD_LOGIC;
QC : In STD_LOGIC;
QR : In STD_LOGIC;
QS : In STD_LOGIC;
AZ : Out STD_LOGIC;
FZ : Out STD_LOGIC;
NZ : Out STD_LOGIC;
OZ : Out STD_LOGIC;
Q2Z : Out STD_LOGIC;
QZ : Out STD_LOGIC );
end component;
begin
qa_r <= qa_r_DUMMY;
qb_r <= qb_r_DUMMY;
qc_r <= qc_r_DUMMY;
qd_r <= qd_r_DUMMY;
I1 : SUPER_LOGIC
Port Map ( A1=>BCD_a, A2=>GND, A3=>ED_a, A4=>GND, A5=>qa_r_DUMMY,
A6=>GND, B1=>ED_a, B2=>qc_r_DUMMY, C1=>qc_r_DUMMY,
C2=>ED_a, D1=>qb_r_DUMMY, D2=>GND, E1=>VCC,
E2=>qb_r_DUMMY, F1=>qc_r_DUMMY, F2=>GND, F3=>qd_r_DUMMY,
F4=>GND, F5=>VCC, F6=>GND, MP=>GND, MS=>qc_r_DUMMY,
NP=>enable, \NS\=>GND, OP=>GND, OS=>GND, PP=>GND,
PS=>GND, QC=>clk, QR=>clear, QS=>GND, AZ=>ABCDE_a,
FZ=>open, NZ=>open, OZ=>open, Q2Z=>qb_r_DUMMY,
QZ=>qc_r_DUMMY );
I2 : SUPER_LOGIC
Port Map ( A1=>enable, A2=>GND, A3=>qd_r_DUMMY, A4=>GND, A5=>VCC,
A6=>GND, B1=>qa_r_DUMMY, B2=>GND, C1=>VCC,
C2=>qa_r_DUMMY, D1=>enable, D2=>qd_r_DUMMY,
E1=>qd_r_DUMMY, E2=>enable, F1=>qb_r_DUMMY, F2=>GND,
F3=>qc_r_DUMMY, F4=>GND, F5=>qd_r_DUMMY, F6=>GND,
MP=>enable, MS=>GND, NP=>GND, \NS\=>qd_r_DUMMY, OP=>GND,
OS=>GND, PP=>GND, PS=>GND, QC=>clk, QR=>clear, QS=>GND,
AZ=>ED_a, FZ=>BCD_a, NZ=>open, OZ=>open,
Q2Z=>qd_r_DUMMY, QZ=>qa_r_DUMMY );
end SCHEMATIC;
library IEEE;
use IEEE.std_logic_1164.all;
entity COUNTER_EN_8BIT_III_S is
Port ( clear : In STD_LOGIC;
clk : In STD_LOGIC;
enable : In STD_LOGIC;
enable_1 : In STD_LOGIC;
enable_2 : In STD_LOGIC;
enable_3 : In STD_LOGIC;
enable_4 : In STD_LOGIC;
count : Out STD_LOGIC_VECTOR (7 downto 0);
enable_5_r : Out STD_LOGIC;
enable_6_r : Out STD_LOGIC );
end COUNTER_EN_8BIT_III_S;
architecture SCHEMATIC of COUNTER_EN_8BIT_III_S is
attribute syn_macro : integer;
attribute syn_macro of SCHEMATIC : architecture is 1;
signal enable_in2_a : STD_LOGIC;
signal enable_in1_a : STD_LOGIC;
constant VCC : STD_LOGIC := '1';
constant GND : STD_LOGIC := '0';
signal count_DUMMY : STD_LOGIC_VECTOR (7 downto 0);
signal enable_5_r_DUMMY : STD_LOGIC;
signal enable_6_r_DUMMY : STD_LOGIC;
component COUNTER_EN_4BIT_S
Port ( clear : In STD_LOGIC;
clk : In STD_LOGIC;
enable : In STD_LOGIC;
qa_r : Out STD_LOGIC;
qb_r : Out STD_LOGIC;
qc_r : Out STD_LOGIC;
qd_r : Out STD_LOGIC );
end component;
component SUPER_LOGIC
Port ( A1 : In STD_LOGIC;
A2 : In STD_LOGIC;
A3 : In STD_LOGIC;
A4 : In STD_LOGIC;
A5 : In STD_LOGIC;
A6 : In STD_LOGIC;
B1 : In STD_LOGIC;
B2 : In STD_LOGIC;
C1 : In STD_LOGIC;
C2 : In STD_LOGIC;
D1 : In STD_LOGIC;
D2 : In STD_LOGIC;
E1 : In STD_LOGIC;
E2 : In STD_LOGIC;
F1 : In STD_LOGIC;
F2 : In STD_LOGIC;
F3 : In STD_LOGIC;
F4 : In STD_LOGIC;
F5 : In STD_LOGIC;
F6 : In STD_LOGIC;
MP : In STD_LOGIC;
MS : In STD_LOGIC;
NP : In STD_LOGIC;
\NS\ : In STD_LOGIC;
OP : In STD_LOGIC;
OS : In STD_LOGIC;
PP : In STD_LOGIC;
PS : In STD_LOGIC;
QC : In STD_LOGIC;
QR : In STD_LOGIC;
QS : In STD_LOGIC;
AZ : Out STD_LOGIC;
FZ : Out STD_LOGIC;
NZ : Out STD_LOGIC;
OZ : Out STD_LOGIC;
Q2Z : Out STD_LOGIC;
QZ : Out STD_LOGIC );
end component;
begin
count(7 downto 0) <= count_DUMMY(7 downto 0);
enable_5_r <= enable_5_r_DUMMY;
enable_6_r <= enable_6_r_DUMMY;
I17 : COUNTER_EN_4BIT_S
Port Map ( clear=>clear, clk=>clk, enable=>enable_in1_a,
qa_r=>count_DUMMY(3), qb_r=>count_DUMMY(2),
qc_r=>count_DUMMY(1), qd_r=>count_DUMMY(0) );
I18 : COUNTER_EN_4BIT_S
Port Map ( clear=>clear, clk=>clk, enable=>enable_in2_a,
qa_r=>count_DUMMY(7), qb_r=>count_DUMMY(6),
qc_r=>count_DUMMY(5), qd_r=>count_DUMMY(4) );
I16 : SUPER_LOGIC
Port Map ( A1=>enable, A2=>gnd, A3=>enable_1, A4=>gnd,
A5=>enable_2, A6=>gnd, B1=>gnd, B2=>gnd, C1=>vcc,
C2=>gnd, D1=>enable_4, D2=>gnd, E1=>vcc, E2=>gnd,
F1=>enable_in1_a, F2=>gnd, F3=>enable_5_r_DUMMY,
F4=>gnd, F5=>vcc, F6=>gnd, MP=>gnd, MS=>gnd, NP=>gnd,
\NS\=>gnd, OP=>enable_3, OS=>gnd, PP=>gnd, PS=>gnd,
QC=>clk, QR=>clear, QS=>gnd, AZ=>open, FZ=>enable_in2_a,
NZ=>open, OZ=>enable_in1_a, Q2Z=>open, QZ=>open );
I15 : SUPER_LOGIC
Port Map ( A1=>count_DUMMY(3), A2=>gnd, A3=>count_DUMMY(2),
A4=>gnd, A5=>count_DUMMY(1), A6=>gnd, B1=>gnd, B2=>gnd,
C1=>vcc, C2=>gnd, D1=>count_DUMMY(0), D2=>gnd, E1=>vcc,
E2=>gnd, F1=>vcc, F2=>gnd, F3=>vcc, F4=>gnd, F5=>vcc,
F6=>gnd, MP=>gnd, MS=>gnd, NP=>gnd, \NS\=>gnd, OP=>vcc,
OS=>gnd, PP=>gnd, PS=>gnd, QC=>clk, QR=>clear, QS=>gnd,
AZ=>open, FZ=>open, NZ=>open, OZ=>open, Q2Z=>open,
QZ=>enable_5_r_DUMMY );
I12 : SUPER_LOGIC
Port Map ( A1=>count_DUMMY(7), A2=>gnd, A3=>count_DUMMY(6),
A4=>gnd, A5=>count_DUMMY(5), A6=>gnd, B1=>gnd, B2=>gnd,
C1=>vcc, C2=>gnd, D1=>count_DUMMY(4), D2=>gnd, E1=>vcc,
E2=>gnd, F1=>vcc, F2=>gnd, F3=>vcc, F4=>gnd, F5=>vcc,
F6=>gnd, MP=>gnd, MS=>gnd, NP=>gnd, \NS\=>gnd, OP=>vcc,
OS=>gnd, PP=>gnd, PS=>gnd, QC=>clk, QR=>clear, QS=>gnd,
AZ=>open, FZ=>open, NZ=>open, OZ=>open, Q2Z=>open,
QZ=>enable_6_r_DUMMY );
end SCHEMATIC;
library IEEE;
use IEEE.std_logic_1164.all;
entity COUNTER_EN_8BIT_II_S is
Port ( clear : In STD_LOGIC;
clk : In STD_LOGIC;
enable : In STD_LOGIC;
enable_1 : In STD_LOGIC;
enable_2 : In STD_LOGIC;
count : Out STD_LOGIC_VECTOR (7 downto 0);
enable_3_r : Out STD_LOGIC;
enable_4_r : Out STD_LOGIC );
end COUNTER_EN_8BIT_II_S;
architecture SCHEMATIC of COUNTER_EN_8BIT_II_S is
attribute syn_macro : integer;
attribute syn_macro of SCHEMATIC : architecture is 1;
signal enable_in1_a : STD_LOGIC;
signal enable_in2_a : STD_LOGIC;
constant VCC : STD_LOGIC := '1';
constant GND : STD_LOGIC := '0';
signal count_DUMMY : STD_LOGIC_VECTOR (7 downto 0);
signal enable_3_r_DUMMY : STD_LOGIC;
signal enable_4_r_DUMMY : STD_LOGIC;
component COUNTER_EN_4BIT_S
Port ( clear : In STD_LOGIC;
clk : In STD_LOGIC;
enable : In STD_LOGIC;
qa_r : Out STD_LOGIC;
qb_r : Out STD_LOGIC;
qc_r : Out STD_LOGIC;
qd_r : Out STD_LOGIC );
end component;
component SUPER_LOGIC
Port ( A1 : In STD_LOGIC;
A2 : In STD_LOGIC;
A3 : In STD_LOGIC;
A4 : In STD_LOGIC;
A5 : In STD_LOGIC;
A6 : In STD_LOGIC;
B1 : In STD_LOGIC;
B2 : In STD_LOGIC;
C1 : In STD_LOGIC;
C2 : In STD_LOGIC;
D1 : In STD_LOGIC;
D2 : In STD_LOGIC;
E1 : In STD_LOGIC;
E2 : In STD_LOGIC;
F1 : In STD_LOGIC;
F2 : In STD_LOGIC;
F3 : In STD_LOGIC;
F4 : In STD_LOGIC;
F5 : In STD_LOGIC;
F6 : In STD_LOGIC;
MP : In STD_LOGIC;
MS : In STD_LOGIC;
NP : In STD_LOGIC;
\NS\ : In STD_LOGIC;
OP : In STD_LOGIC;
OS : In STD_LOGIC;
PP : In STD_LOGIC;
PS : In STD_LOGIC;
QC : In STD_LOGIC;
QR : In STD_LOGIC;
QS : In STD_LOGIC;
AZ : Out STD_LOGIC;
FZ : Out STD_LOGIC;
NZ : Out STD_LOGIC;
OZ : Out STD_LOGIC;
Q2Z : Out STD_LOGIC;
QZ : Out STD_LOGIC );
end component;
begin
count(7 downto 0) <= count_DUMMY(7 downto 0);
enable_3_r <= enable_3_r_DUMMY;
enable_4_r <= enable_4_r_DUMMY;
I16 : COUNTER_EN_4BIT_S
Port Map ( clear=>clear, clk=>clk, enable=>enable_in1_a,
qa_r=>count_DUMMY(3), qb_r=>count_DUMMY(2),
qc_r=>count_DUMMY(1), qd_r=>count_DUMMY(0) );
I17 : COUNTER_EN_4BIT_S
Port Map ( clear=>clear, clk=>clk, enable=>enable_in2_a,
qa_r=>count_DUMMY(7), qb_r=>count_DUMMY(6),
qc_r=>count_DUMMY(5), qd_r=>count_DUMMY(4) );
I15 : SUPER_LOGIC
Port Map ( A1=>count_DUMMY(3), A2=>gnd, A3=>count_DUMMY(2),
A4=>gnd, A5=>count_DUMMY(1), A6=>gnd, B1=>gnd, B2=>gnd,
C1=>vcc, C2=>gnd, D1=>count_DUMMY(0), D2=>gnd, E1=>vcc,
E2=>gnd, F1=>enable_1, F2=>gnd, F3=>enable_2, F4=>gnd,
F5=>enable, F6=>gnd, MP=>gnd, MS=>gnd, NP=>gnd,
\NS\=>gnd, OP=>vcc, OS=>gnd, PP=>gnd, PS=>gnd, QC=>clk,
QR=>clear, QS=>gnd, AZ=>open, FZ=>enable_in1_a,
NZ=>open, OZ=>open, Q2Z=>open, QZ=>enable_3_r_DUMMY );
I12 : SUPER_LOGIC
Port Map ( A1=>count_DUMMY(7), A2=>gnd, A3=>count_DUMMY(6),
A4=>gnd, A5=>count_DUMMY(5), A6=>gnd, B1=>gnd, B2=>gnd,
C1=>vcc, C2=>gnd, D1=>count_DUMMY(4), D2=>gnd, E1=>vcc,
E2=>gnd, F1=>enable, F2=>gnd, F3=>enable_in1_a, F4=>gnd,
F5=>enable_3_r_DUMMY, F6=>gnd, MP=>gnd, MS=>gnd,
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