alarmclk.syn

这是一个非常好的VHDL的源码

JDF B
// Created by Version 9.0 
PROJECT Demo
DESIGN alarmclk Normal
DEVKIT ispLSI5384VE-80LF256I
ENTRY ABEL/Schematic
STIMULUS test.abv
STIMULUS alarmclk.wdl
DOCUMENT spec.txt
MODULE alarmclk.sch
MODSTYLE alarmclk Normal
MODULE comptime.abl
MODSTYLE comptime Normal
MODULE dsplymux.sch
MODSTYLE dsplymux Normal
MODULE timestor.abl
MODSTYLE timestor Normal
MODULE alrmstor.sch
MODSTYLE alrmstor Normal
MODULE stor.sch
MODSTYLE stor Normal