sap1.adf

這是用verilog寫的一個簡單的處理器

[Project]
Current Flow=Generic
VCS=0
version=1
modified=9
Current Config=compile
[Configurations]
compile=sap1
[Library]
sap1=.\sap1.LIB
[$LibMap$]
sap1=.
[Settings]
FLOW_TYPE=Schematic
LANGUAGE=VERILOG
FLOWTOOLS=ONLY_IMPL
[IMPLEMENTATION]
UCF=
[Files]
TestBench/SAP_1_TB.v=-1
TestBench/SAP_1_TB_runtest.do=-1
/prom.v=-1
/SAP_1.v=-1
[Files.Data]
.\src\TestBench\SAP_1_TB.v=Verilog Test Bench
.\src\TestBench\SAP_1_TB_runtest.do=Macro
.\src\prom.v=Verilog Source Code
.\src\SAP_1.v=Verilog Source Code
[Groups]
TestBench=1