0.mgf

来自「這是用verilog寫的一個簡單的處理器」· MGF 代码 · 共 260 行

MGF
260 行
字号 
V 000035 12 121 1117617725116 PROME PROM VERILOG L VL;U VL.VERILOG_LOGIC;P ADDR _in wire[3:0]V ADDR - - - -P DATA _out reg[7:0]V DATA - - - -X PROMV 000036 12 180 1117617771904 SAP_1E SAP_1 VERILOG L VL;U VL.VERILOG_LOGIC;P asy_rst _in wireV asy_rst - - - -P clk _in wireV clk - - - -P Oreg _out reg[7:0]V Oreg - - - -P go _in wireV go - - - -X SAP_1V 000036 12 180 1117619581356 SAP_1E SAP_1 VERILOG L VL;U VL.VERILOG_LOGIC;P asy_rst _in wireV asy_rst - - - -P clk _in wireV clk - - - -P Oreg _out reg[7:0]V Oreg - - - -P go _in wireV go - - - -X SAP_1V 000035 12 121 1117619636885 PROME PROM VERILOG L VL;U VL.VERILOG_LOGIC;P ADDR _in wire[3:0]V ADDR - - - -P DATA _out reg[7:0]V DATA - - - -X PROMV 000035 12 121 1117619812548 PROME PROM VERILOG L VL;U VL.VERILOG_LOGIC;P ADDR _in wire[3:0]V ADDR - - - -P DATA _out reg[7:0]V DATA - - - -X PROMV 000038 12 57 1117619814070 SAP_1_tbE SAP_1_tb VERILOG L VL;U VL.VERILOG_LOGIC;X SAP_1_tbV 000036 12 180 1117619820600 SAP_1E SAP_1 VERILOG L VL;U VL.VERILOG_LOGIC;P asy_rst _in wireV asy_rst - - - -P clk _in wireV clk - - - -P Oreg _out reg[7:0]V Oreg - - - -P go _in wireV go - - - -X SAP_1V 000038 12 57 1117619830073 SAP_1_tbE SAP_1_tb VERILOG L VL;U VL.VERILOG_LOGIC;X SAP_1_tbV 000035 12 121 1117620014729 PROME PROM VERILOG L VL;U VL.VERILOG_LOGIC;P ADDR _in wire[3:0]V ADDR - - - -P DATA _out reg[7:0]V DATA - - - -X PROMV 000036 12 180 1117620762053 SAP_1E SAP_1 VERILOG L VL;U VL.VERILOG_LOGIC;P asy_rst _in wireV asy_rst - - - -P clk _in wireV clk - - - -P Oreg _out reg[7:0]V Oreg - - - -P go _in wireV go - - - -X SAP_1V 000035 12 121 1117620807799 PROME PROM VERILOG L VL;U VL.VERILOG_LOGIC;P ADDR _in wire[3:0]V ADDR - - - -P DATA _out reg[7:0]V DATA - - - -X PROMV 000038 12 57 1117620810373 SAP_1_tbE SAP_1_tb VERILOG L VL;U VL.VERILOG_LOGIC;X SAP_1_tbV 000036 12 180 1117620814058 SAP_1E SAP_1 VERILOG L VL;U VL.VERILOG_LOGIC;P asy_rst _in wireV asy_rst - - - -P clk _in wireV clk - - - -P Oreg _out reg[7:0]V Oreg - - - -P go _in wireV go - - - -X SAP_1V 000038 12 57 1117620822190 SAP_1_tbE SAP_1_tb VERILOG L VL;U VL.VERILOG_LOGIC;X SAP_1_tbV 000035 12 121 1117620947810 PROME PROM VERILOG L VL;U VL.VERILOG_LOGIC;P ADDR _in wire[3:0]V ADDR - - - -P DATA _out reg[7:0]V DATA - - - -X PROMV 000035 12 121 1117624186768 PROME PROM VERILOG L VL;U VL.VERILOG_LOGIC;P ADDR _in wire[3:0]V ADDR - - - -P DATA _out reg[7:0]V DATA - - - -X PROMV 000036 12 180 1117624199026 SAP_1E SAP_1 VERILOG L VL;U VL.VERILOG_LOGIC;P asy_rst _in wireV asy_rst - - - -P clk _in wireV clk - - - -P Oreg _out reg[7:0]V Oreg - - - -P go _in wireV go - - - -X SAP_1V 000038 12 57 1117624202631 SAP_1_tbE SAP_1_tb VERILOG L VL;U VL.VERILOG_LOGIC;X SAP_1_tbV 000036 12 180 1117624382319 SAP_1E SAP_1 VERILOG L VL;U VL.VERILOG_LOGIC;P asy_rst _in wireV asy_rst - - - -P clk _in wireV clk - - - -P Oreg _out reg[7:0]V Oreg - - - -P go _in wireV go - - - -X SAP_1V 000038 12 57 1117624386265 SAP_1_tbE SAP_1_tb VERILOG L VL;U VL.VERILOG_LOGIC;X SAP_1_tbV 000035 12 121 1117624478858 PROME PROM VERILOG L VL;U VL.VERILOG_LOGIC;P ADDR _in wire[3:0]V ADDR - - - -P DATA _out reg[7:0]V DATA - - - -X PROMV 000036 12 180 1117624597519 SAP_1E SAP_1 VERILOG L VL;U VL.VERILOG_LOGIC;P asy_rst _in wireV asy_rst - - - -P clk _in wireV clk - - - -P Oreg _out reg[7:0]V Oreg - - - -P go _in wireV go - - - -X SAP_1V 000036 12 180 1117625065091 SAP_1E SAP_1 VERILOG L VL;U VL.VERILOG_LOGIC;P asy_rst _in wireV asy_rst - - - -P clk _in wireV clk - - - -P Oreg _out reg[7:0]V Oreg - - - -P go _in wireV go - - - -X SAP_1V 000036 12 180 1117625125197 SAP_1E SAP_1 VERILOG L VL;U VL.VERILOG_LOGIC;P asy_rst _in wireV asy_rst - - - -P clk _in wireV clk - - - -P Oreg _out reg[7:0]V Oreg - - - -P go _in wireV go - - - -X SAP_1V 000035 12 121 1117625250387 PROME PROM VERILOG L VL;U VL.VERILOG_LOGIC;P ADDR _in wire[3:0]V ADDR - - - -P DATA _out reg[7:0]V DATA - - - -X PROMV 000036 12 180 1117625255425 SAP_1E SAP_1 VERILOG L VL;U VL.VERILOG_LOGIC;P asy_rst _in wireV asy_rst - - - -P clk _in wireV clk - - - -P Oreg _out reg[7:0]V Oreg - - - -P go _in wireV go - - - -X SAP_1V 000038 12 57 1117625256176 SAP_1_tbE SAP_1_tb VERILOG L VL;U VL.VERILOG_LOGIC;X SAP_1_tb

0.mgf - 源码说明

本页面展示了「這是用verilog寫的一個簡單的處理器」中的 0.mgf 源码文件，采用 MGF 编程语言编写，共 260 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

虫虫开发者社区收录了大量与Verilog相关的技术资源，包括源代码、技术文档、电路图等，是电子工程师和嵌入式开发者的专业学习平台。

⌨️ 快捷键说明

复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?